Today at a Glance

▸ Phase 1 of 5  ·  ~5 min

🌍 Contextualize

A Barcelona hook for today's concept

You're Studying HDL in Gaudí's City

▸ Phase 2 of 5  ·  ~30 min  ·  Setup-heavy on Day 1

⚠️ Reframe

Sharper lens on the pre-class video + getting everyone onto silicon

⚠️ If You're Thinking Like a Programmer…

Two Paths from One Source

Toolchain Health Check

Run these in order. Everyone gets a green line for each before lab starts.

yosys -V              # synthesis
nextpnr-ice40 --version  # place & route
icepack -h            # bitstream packer
iverilog -V           # simulation
iceprog               # USB programmer (errors w/o board — that's OK)

Instructor at the back walks any laptop that fails — no one moves to Assemble without a working chain.

Anatomy of a Module

// led_on.v — the simplest possible design
module led_on (
    output wire o_LED_1   // a single pin on the chip
);
    assign o_LED_1 = 1'b1;  // continuously drive HIGH
endmodule

• Module = chip on a board. Ports are pins, not function arguments.
• assign = a wire. It is always driven, not "called."
• .pcf file = the soldering. Maps o_LED_1 to the FPGA pin connected to LED1 on the Go Board.

▸ Phase 3 of 5  ·  ~65 min  ·  You build

🛠 Assemble

Write code, run sims, flash the board

Build Plan — Three Increments

1. Ex 2 · 15 min  LED On — hardwire o_LED_1 = 1'b1. Full synth → place & route → bitstream → program. First win: a lit LED.
2. Ex 3 · 25 min  Buttons → LEDs — four assign statements wire each switch to its LED. First taste of multi-port modules.
3. Ex 4 · 20 min  Logic mods — invert, AND, OR, XOR. Predict, then observe how the LEDs change.

Live Demo Cue — One-Liner First

// Instructor types live, then runs the full flow
module led_on (output wire o_LED_1);
    assign o_LED_1 = 1'b1;
endmodule

yosys -p "synth_ice40 -top led_on -json led_on.json" led_on.v
nextpnr-ice40 --hx1k --package vq100 --pcf go_board.pcf \
              --json led_on.json --asc led_on.asc
icepack led_on.asc led_on.bin
iceprog led_on.bin   # 🎉 LED1 lights

After this, students run their own through the same flow. The Makefile in Ex 5 wraps all four commands into make prog.

Buttons → LEDs (Lab Ex 3 starter)

module buttons_to_leds (
    input  wire i_Switch_1, i_Switch_2, i_Switch_3, i_Switch_4,
    output wire o_LED_1,    o_LED_2,    o_LED_3,    o_LED_4
);
    assign o_LED_1 = i_Switch_1;
    assign o_LED_2 = i_Switch_2;
    assign o_LED_3 = i_Switch_3;
    assign o_LED_4 = i_Switch_4;
endmodule

When this works, swap one assign for ~, &, |, or ^ — that's Ex 4.

▸ Phase 4 of 5  ·  ~35 min  ·  Verify, test, harden

🛡 Fortify

Don't trust a blink — prove it

Simulation Before Silicon

cd labs/week1_day01/ex3_button_logic/starter
make sim    # expect "16 passed, 0 failed"
make wave   # opens GTKWave for visual debug

Hardware Verification Checklist

• Each switch lights its LED? All four directions covered.
• Inverted LED is on when switch is off? Confirms ~ reached silicon.
• AND/OR/XOR outputs match the truth table? Step through every input combo.
• Pressing two buttons at once works as expected? No glitches, no flicker.
• Response feels instant? Good — that's combinational. Day 4 will show why sequential logic feels different.

Common Day-1 Pitfalls

If you can't reproduce a bug in make sim, it's almost always a driver, pin, or polarity issue — not your Verilog.

▸ Phase 5 of 5  ·  ~15 min

🔗 Transfer

What generalizes? Where will you use this next?

What You Learned That Generalizes

Next, Same Session → Data Types & Vectors