Today at a Glance

▸ Phase 1 of 5  ·  ~10 min

🌍 Contextualize

Barcelona on a clock

The City on a Clock Edge

▸ Phase 2 of 5  ·  ~15 min

⚠️ Reframe

The one rule that prevents almost every Day-4 bug

⚠️ Order Doesn't Mean Order

Blocking vs. Nonblocking — the Picture

RTL: Count the Flip-Flops

always @(posedge clk) begin
    if (rst) begin
        q1 <= 0;        // ← FF #1
        q2 <= 0;        // ← FF #2
        cnt <= 0;       // ← FFs (one per bit of cnt)
    end else begin
        q1  <= d;
        q2  <= q1;      // shift-register stage
        cnt <= cnt + 1;
    end
end

Three <= targets ⇒ three storage elements. cnt is N flip-flops where N = bit-width.

▸ Phase 3 of 5  ·  ~70 min  ·  You build

🛠 Assemble

From one FF to a visible blinker

Build Plan

1. Ex 1 · 15 min  D flip-flop — synchronous reset, posedge-only update. Sim first.
2. Ex 2 · 15 min  Loadable register — add en and load. Implicit feedback when disabled.
3. Ex 3 · 15 min  Free-running counter — N-bit up-counter with terminal-count output.
4. Ex 4 · 20 min  LED blinker — clock divider — 25 MHz ÷ 25 000 000 = 1 Hz. The first design where you can see hardware time.

D Flip-Flop — Canonical Form

module dff (
    input  wire clk, rst, d,
    output reg  q
);
    always @(posedge clk) begin
        if (rst) q <= 1'b0;
        else     q <= d;
    end
endmodule

Three lines of behavior. One flip-flop in the netlist. This is the atom of all sequential logic.

LED Blinker — Hardware Time

module blinker (
    input  wire clk,            // 25 MHz from Go Board
    output reg  led
);
    localparam HALF_PERIOD = 12_500_000;   // 0.5 s
    reg [23:0] cnt;

    always @(posedge clk) begin
        if (cnt == HALF_PERIOD - 1) begin
            cnt <= 0;
            led <= ~led;
        end else begin
            cnt <= cnt + 1;
        end
    end
endmodule

24-bit counter (2²⁴ = 16 777 216 > 12 500 000). The toggle pattern is the canonical "slow event from a fast clock."

▸ Phase 4 of 5  ·  ~45 min  ·  Verify · waveform · AI check

🛡 Fortify

Sequential logic earns sequential proof

Sim First — Waveforms Tell the Truth

cd labs/week1_day04/ex1_dff/starter
iverilog -o dff_tb dff.v dff_tb.v
vvp dff_tb           # generates dump.vcd
gtkwave dump.vcd     # add clk, d, q to viewer

• Does q change only on the rising edge of clk? Look — don't assume.
• Does q sample the value of d at the edge, not before or after?
• Does reset force q low immediately on the next edge?
• For the blinker: shrink HALF_PERIOD to 5 in sim — watch the counter wrap and the LED toggle.

🤖 Check the Machine (first time!)

• Does the answer match what you learned? Where exactly is it imprecise?
• Does it warn about simulation-synthesis mismatch when you mix them?
• Does it explicitly say: "= in always @(*), <= in always @(posedge clk)"?
• Save the prompt + reply to your AI workflow portfolio (this is graded — 8% of the course).

Hardware Verification

• D-FF on board: press button rapidly — LED updates only on clock edges (you won't see flicker because 25 MHz >> eye).
• Loadable register: hold en low → output frozen even when d changes.
• Counter: wire bottom 4 bits to LEDs (a slow-clock version) — binary count visible.
• Blinker: ~1 Hz toggle on LED 0. Time it with a phone stopwatch — should be within ±1%.

▸ Phase 5 of 5  ·  ~10 min  ·  Week 1 closes

🔗 Transfer

What four days bought you

Week 1 Recap

Weekend → Week 2 Prep