Barcelona Abroad · Week 2 · Day 7

Finite State Machines

CRAFT cycle · 2.5 hours · Tue 6/2 · PM visit: HP Barcelona

HDL for Digital System Design · UCF ECE · Barcelona Summer 2026

CRAFT

Today at a Glance

PhaseTimeActivity
🌍 Contextualize10 minFSMs in the metro · Semidynamics debrief
⚠️ Reframe15 min3 always blocks ↔ 3 physical pieces · Moore vs Mealy
🛠 Assemble70 minTraffic light FSM · TB for every transition · pattern detector
🛡 Fortify45 minState-coverage sweep · timing check · AI-generated FSM critique
🔗 Transfer10 minBrief for HP · D8 preview
Today's mental model: an FSM is hardware that remembers. Three blocks describe it. One TB proves it.

▸ Phase 1 of 5  ·  ~10 min

🌍 Contextualize

State machines run the city

FSMs Are Everywhere You Looked Yesterday

  • Metro train door controller — CLOSED → OPENING → OPEN → CLOSING → CLOSED
  • Traffic light at Plaça Catalunya — GREEN → YELLOW → RED, with pedestrian button as input
  • Vending machine at the airport — IDLE → COIN → SELECT → DISPENSE
  • Semidynamics pipeline control (yesterday's visit) — FETCH → DECODE → EXEC → MEM → WB

Semidynamics debrief — 60 sec

Whose CRAFT reflection mentioned an FSM at Semidynamics? Share one. (Tee it up: today is where their pipeline diagrams become your Verilog.)

An FSM is the moment HDL becomes controllable — it's how a circuit decides what to do next.

▸ Phase 2 of 5  ·  ~15 min

⚠️ Reframe

The 3-block pattern is the hardware

⚠️ An FSM Is Not a switch Statement

❌ Wrong Model

"It's a switch inside a while(1). Same as software."

✓ Right Model

An FSM is three physical things: flip-flops holding state · combinational logic computing next state · combinational logic computing outputs. The 3-always-block code style maps 1-to-1 onto those three pieces.

Three always blocks. Three concerns. Don't mix them.

Three Pieces of Hardware

FSM block diagram: a state register (flip-flops) feeds next-state logic and output logic; next-state logic feeds back into the state register
State register
sequential · always @(posedge clk)
Next-state & output logic
combinational · always @(*)

The 3-Block FSM Skeleton

Traffic light state diagram: GREEN to YELLOW to RED and back to GREEN, each transition firing when its timer is done
localparam GREEN = 2'd0, YELLOW = 2'd1, RED = 2'd2;
reg [1:0] state, next;

// Block 1: state register — sequential, the only @(posedge clk)
always @(posedge clk)
    if (rst) state <= GREEN;
    else     state <= next;

// Block 2: next-state logic — combinational, depends on state + inputs
always @(*) begin
    next = state;                                    // safe default — no latch
    case (state)
        GREEN:  if (green_timer_done)  next = YELLOW;
        YELLOW: if (yellow_timer_done) next = RED;
        RED:    if (red_timer_done)    next = GREEN;
    endcase
end

// Block 3: output logic — combinational, depends on state (Moore)
always @(*) begin
    {led_g, led_y, led_r} = 3'b000;                  // default
    case (state)
        GREEN:  led_g = 1'b1;
        YELLOW: led_y = 1'b1;
        RED:    led_r = 1'b1;
    endcase
end

Memorize this layout. Every FSM you write this course follows it.

Moore vs Mealy in One Slide

Moore

Outputs depend on state only.

  • Glitch-free outputs (registered behavior)
  • Easier to reason about, easier to verify
  • Default choice for control FSMs

Mealy

Outputs depend on state + input.

  • Fewer states needed
  • Can output one cycle earlier
  • Easy to introduce hazards — use deliberately
Today's traffic light is Moore. The stretch pattern detector is your first Mealy.

▸ Phase 3 of 5  ·  ~70 min  ·  You build

🛠 Assemble

Diagram → table → code → board

Build Plan

  1. Ex 1 · 30 min  Traffic light controller — 3 states, parameterized timers, LEDs on the Go Board.
  2. Ex 2 · 20 min  Traffic light TB — verify the full cycle, timing, and reset behavior.
  3. Ex 3 · 20 min  Pattern detector "1101" — Moore version. A state per bit of progress.
Stretch (Ex 4): Re-implement the pattern detector as a Mealy machine. Compare state count and output timing on GTKWave.
The discipline: draw the state diagram on paper before you touch the keyboard. Every time.

State Diagram → State Table → Code

State diagram for a 1101 sequence detector: states S0 through S4 with transitions on input 0 and 1; S4 asserts the found output

State table — pattern detector "1101"

Statein=0in=1out
S0S0S10
S1S0S20
S2 (11)S3S20
S3 (110)S0S40
S4 (1101)S0S11

From the table, the Verilog writes itself:

case (state)
    S0: next = in ? S1 : S0;
    S1: next = in ? S2 : S0;
    S2: next = in ? S2 : S3;
    S3: next = in ? S4 : S0;
    S4: next = in ? S1 : S0;
endcase

Output: found = (state == S4);

Traffic Light TB — State Coverage

// Use SHORT timers in sim — match the parameter name
traffic_light #(
    .GREEN_TIME(10), .YELLOW_TIME(5), .RED_TIME(15)
) dut (.clk(clk), .rst(rst), .led_g(g), .led_y(y), .led_r(r));

initial begin
    rst = 1; #20; rst = 0;
    // Expect GREEN for 10 cycles
    repeat (10) @(posedge clk);
    if ({g,y,r} !== 3'b100) $display("FAIL: not GREEN after rst");
    // Expect YELLOW for 5 cycles
    repeat (5)  @(posedge clk);
    if ({g,y,r} !== 3'b010) $display("FAIL: did not enter YELLOW");
    // Expect RED for 15 cycles
    repeat (15) @(posedge clk);
    if ({g,y,r} !== 3'b001) $display("FAIL: did not enter RED");
    // Back to GREEN
    @(posedge clk);
    if ({g,y,r} !== 3'b100) $display("FAIL: did not return to GREEN");
    $display("PASS"); $finish;
end

Notice the parameter override — same TB stays usable when you flash with the long hardware timers.

▸ Phase 4 of 5  ·  ~45 min  ·  Verify · harden · critique AI

🛡 Fortify

Every state. Every transition. Both blocks reachable.

The FSM Verification Checklist

  • State reachability: does every state get entered during the TB? If not, add stimulus.
  • Transition coverage: every arrow in your diagram exercised at least once.
  • Reset from every state: assert rst mid-run, confirm return to the reset state.
  • Unreachable states are safe: hit default in case — output should be benign, not X.
  • Timing: each state lasts exactly the expected number of cycles (use parameterized sim timers).
Open GTKWave on state, next, and inputs together — the diagram comes alive.

🤖 Check the Machine — FSM Prompt

Prompt: "Generate a Verilog FSM for a traffic light controller with a pedestrian button input that forces a quick yellow + red cycle. Use the 3-always-block pattern."

  • Did it use 3 always blocks? Or did it cram everything into one @(posedge clk)?
  • Is the next-state block latch-free? Look for a next = state; default at the top.
  • Does the pedestrian button get debounced and synchronized? If not, that's a real-world bug — the AI's lab works only in sim.
  • Refactor what's wrong, save the prompt + before/after to your portfolio.
Common AI sin: declaring state with a blocking assignment in @(posedge clk). That's a sim/synth mismatch waiting to bite you.

Hardware Verification

  • Traffic light on the Go Board: LEDs cycle green → yellow → red at human-visible cadence. Phone-stopwatch the green duration — should match your parameter.
  • Pattern detector: drive the input with a switch + button, press the sequence 1-1-0-1 — the "found" LED pulses for one cycle.
  • False sequences do not trigger: 1-1-0-0, 1-0-1, 0-1-1-0-1 — all should stay dark.
Why this matters: the FSM is now controlling outputs based on stateful history. Every protocol — UART, SPI, AXI handshake — is this pattern, scaled up.

▸ Phase 5 of 5  ·  ~10 min

🔗 Transfer

Carry it to HP this afternoon

At HP Barcelona This Afternoon

HP's Customer Center is about AI-assisted product workflows. The questions to bring:

  1. Where is AI assisting, not replacing? What decisions still belong to humans? (Same question you answered for your AI TB this morning.)
  2. How do they validate AI-generated outputs? Is there a "TB layer" for AI recommendations?
  3. What FSMs run their products? Print job scheduling · firmware update sequencing · power-state controllers — all FSMs.
The link: Semidynamics (yesterday) and HP (today) frame opposite ends of the silicon-to-product chain. Both rely on the same primitives you wrote today.

Tomorrow → Hierarchy & Parameters

D8 is the day you stop copy-pasting modules. Parameters + generate let one module become an entire family.

You'll build a parameterized N-bit counter, instantiate it at 4 different widths, and start tracking PPA — area vs width — for real.

D8 prep tonight

  • 📺 D8 video (~50 min — includes the new recursive-generate segment)
  • 📝 D8 pre-class quiz
  • 📝 HP reflection (1 page, due before D8)

🔗 End of Day 7 · HP Customer Center this afternoon

Three blocks. Three concerns. One FSM.

You can now translate a state diagram to working hardware and prove every transition.
Tomorrow we make those modules reusable.

CRAFT