CRAFT cycle · 2.5 hours · Tue 6/2 · PM visit: HP Barcelona
HDL for Digital System Design · UCF ECE · Barcelona Summer 2026
| Phase | Time | Activity |
|---|---|---|
| 🌍 Contextualize | 10 min | FSMs in the metro · Semidynamics debrief |
| ⚠️ Reframe | 15 min | 3 always blocks ↔ 3 physical pieces · Moore vs Mealy |
| 🛠 Assemble | 70 min | Traffic light FSM · TB for every transition · pattern detector |
| 🛡 Fortify | 45 min | State-coverage sweep · timing check · AI-generated FSM critique |
| 🔗 Transfer | 10 min | Brief for HP · D8 preview |
▸ Phase 1 of 5 · ~10 min
State machines run the city
Whose CRAFT reflection mentioned an FSM at Semidynamics? Share one. (Tee it up: today is where their pipeline diagrams become your Verilog.)
An FSM is the moment HDL becomes controllable — it's how a circuit decides what to do next.
▸ Phase 2 of 5 · ~15 min
The 3-block pattern is the hardware
switch Statement"It's a switch inside a while(1). Same as software."
An FSM is three physical things: flip-flops holding state · combinational logic computing next state · combinational logic computing outputs. The 3-always-block code style maps 1-to-1 onto those three pieces.
always @(posedge clk)always @(*)localparam GREEN = 2'd0, YELLOW = 2'd1, RED = 2'd2;
reg [1:0] state, next;
// Block 1: state register — sequential, the only @(posedge clk)
always @(posedge clk)
if (rst) state <= GREEN;
else state <= next;
// Block 2: next-state logic — combinational, depends on state + inputs
always @(*) begin
next = state; // safe default — no latch
case (state)
GREEN: if (green_timer_done) next = YELLOW;
YELLOW: if (yellow_timer_done) next = RED;
RED: if (red_timer_done) next = GREEN;
endcase
end
// Block 3: output logic — combinational, depends on state (Moore)
always @(*) begin
{led_g, led_y, led_r} = 3'b000; // default
case (state)
GREEN: led_g = 1'b1;
YELLOW: led_y = 1'b1;
RED: led_r = 1'b1;
endcase
end
Memorize this layout. Every FSM you write this course follows it.
Outputs depend on state only.
Outputs depend on state + input.
▸ Phase 3 of 5 · ~70 min · You build
Diagram → table → code → board
State table — pattern detector "1101"
| State | in=0 | in=1 | out |
|---|---|---|---|
| S0 | S0 | S1 | 0 |
| S1 | S0 | S2 | 0 |
| S2 (11) | S3 | S2 | 0 |
| S3 (110) | S0 | S4 | 0 |
| S4 (1101) | S0 | S1 | 1 |
From the table, the Verilog writes itself:
case (state)
S0: next = in ? S1 : S0;
S1: next = in ? S2 : S0;
S2: next = in ? S2 : S3;
S3: next = in ? S4 : S0;
S4: next = in ? S1 : S0;
endcase
Output: found = (state == S4);
// Use SHORT timers in sim — match the parameter name
traffic_light #(
.GREEN_TIME(10), .YELLOW_TIME(5), .RED_TIME(15)
) dut (.clk(clk), .rst(rst), .led_g(g), .led_y(y), .led_r(r));
initial begin
rst = 1; #20; rst = 0;
// Expect GREEN for 10 cycles
repeat (10) @(posedge clk);
if ({g,y,r} !== 3'b100) $display("FAIL: not GREEN after rst");
// Expect YELLOW for 5 cycles
repeat (5) @(posedge clk);
if ({g,y,r} !== 3'b010) $display("FAIL: did not enter YELLOW");
// Expect RED for 15 cycles
repeat (15) @(posedge clk);
if ({g,y,r} !== 3'b001) $display("FAIL: did not enter RED");
// Back to GREEN
@(posedge clk);
if ({g,y,r} !== 3'b100) $display("FAIL: did not return to GREEN");
$display("PASS"); $finish;
end
Notice the parameter override — same TB stays usable when you flash with the long hardware timers.
▸ Phase 4 of 5 · ~45 min · Verify · harden · critique AI
Every state. Every transition. Both blocks reachable.
rst mid-run, confirm return to the reset state.default in case — output should be benign, not X.state, next, and inputs together — the diagram comes alive.
Prompt: "Generate a Verilog FSM for a traffic light controller with a pedestrian button input that forces a quick yellow + red cycle. Use the 3-always-block pattern."
@(posedge clk)?next = state; default at the top.state with a blocking assignment in @(posedge clk). That's a sim/synth mismatch waiting to bite you.
▸ Phase 5 of 5 · ~10 min
Carry it to HP this afternoon
HP's Customer Center is about AI-assisted product workflows. The questions to bring:
D8 is the day you stop copy-pasting modules. Parameters + generate let one module become an entire family.
You'll build a parameterized N-bit counter, instantiate it at 4 different widths, and start tracking PPA — area vs width — for real.
🔗 End of Day 7 · HP Customer Center this afternoon
You can now translate a state diagram to working hardware and prove every transition.
Tomorrow we make those modules reusable.