Today at a Glance

▸ Phase 1 of 5  ·  ~10 min

🌍 Contextualize

Companies ship parameter families, not single modules

Why Companies Parameterize

Today you build your first parameter family. By Week 4 your whole project is parameterized.

▸ Phase 2 of 5  ·  ~15 min

⚠️ Reframe

When the loop runs matters more than what it does

⚠️ generate Is Not a Runtime Loop

generate Unrolls Into Hardware

Parameterized N-Bit Counter

module counter #(
    parameter WIDTH = 8
)(
    input  wire             clk, rst, en,
    output reg  [WIDTH-1:0] q,
    output wire             rollover
);
    assign rollover = (q == {WIDTH{1'b1}}) & en;

    always @(posedge clk) begin
        if (rst)     q <= 0;
        else if (en) q <= q + 1'b1;
    end
endmodule

// Instantiate three sizes from one module:
counter #(.WIDTH(4))  c4  (.clk(clk), .rst(rst), .en(en), .q(q4),  .rollover(r4));
counter #(.WIDTH(8))  c8  (.clk(clk), .rst(rst), .en(en), .q(q8),  .rollover(r8));
counter #(.WIDTH(16)) c16 (.clk(clk), .rst(rst), .en(en), .q(q16), .rollover(r16));

One module · three width-specific netlists. The synthesizer specializes each one.

generate for & generate if

// generate for: replicate hardware
genvar i;
generate
    for (i = 0; i < NUM_LEDS; i = i + 1) begin : g_blink
        blinker #(.PERIOD(1_000_000 * (i+1))) b
            (.clk(clk), .led(leds[i]));
    end
endgenerate

// generate if: include features conditionally
generate
    if (HAS_PARITY) begin : g_parity
        wire par = ^data;                 // XOR-reduce
        assign tx = {par, data};
    end else begin : g_no_parity
        assign tx = data;
    end
endgenerate

▸ Phase 3 of 5  ·  ~70 min  ·  You build · across widths

🛠 Assemble

One module · four widths · one top

Build Plan

1. Ex 1 · 20 min  Parameterized counter — synth at WIDTH = 4, 8, 16, 32. Three instances in one top.
2. Ex 2 · 🤖 25 min  AI-assisted param TB — prompt AI to write a TB that overrides WIDTH and tests rollover at 2^WIDTH - 1. Critique & fix.
3. Ex 3 · 15 min  generate for LED driver — 4 blinkers, period scales with index.
4. Ex 4 · 10 min  Hierarchical top — debouncer (D5) + counter (today) + 7-seg (D2) wired together.

🤖 AI-Assisted Param TB — The Prompt

Write a self-checking Icarus-compatible testbench for this counter module:

  module counter #(parameter WIDTH=8) (
    input clk, rst, en, output [WIDTH-1:0] q, output rollover);

Requirements:
  - Test WIDTH = 4, 8, and 16 in the SAME testbench using #(.WIDTH(N)) overrides
  - For each instance, verify rollover fires at q == (2**WIDTH - 1)
  - Verify reset clears q to 0 from any value
  - Verify en=0 freezes q
  - Use !== for comparisons, print PASS/FAIL summary, $finish at end
  - Target IEEE 1364-2005 Verilog (no SystemVerilog)

• Does the AI use 2**WIDTH - 1 per instance, or hardcode 255? Hardcoding is the #1 failure mode.
• Does it pass three independent DUTs, or one DUT three times? The whole point is separate netlists.
• Save prompt + correction to the AI portfolio.

Hierarchical Top — Composition Pays Off

module lab_instrument (
    input  wire clk,
    input  wire btn_async,
    output wire [6:0] seg
);
    wire btn_clean, tick;
    wire [3:0] count;

    debouncer #(.THRESHOLD(250_000))      u_db   (.clk(clk), .in_async(btn_async),
                                                  .out_clean(btn_clean));
    counter   #(.WIDTH(4))                u_cnt  (.clk(clk), .rst(1'b0), .en(btn_clean),
                                                  .q(count), .rollover());
    hex_to_7seg                           u_disp (.hex(count), .seg(seg));
endmodule

Three modules. Three days of work. Composed in 10 lines. This is the payoff for hierarchy.

▸ Phase 4 of 5  ·  ~45 min  ·  Verify · measure PPA · harden

🛡 Fortify

Make the synthesizer show you the cost

Width Sweep — Capture the Table

for W in 4 8 16 32; do
    yosys -p "read_verilog -DWIDTH=$W counter.v; \
              synth_ice40 -top counter; stat" \
          2>&1 | grep -E "SB_LUT4|SB_DFF"
done

Fill in the table together on the projector:

The PPA Habit Starts Here

Hardware Verification

• Hierarchical top: press the debounced button — 7-seg counts 0 → F → 0 cleanly. One press = one increment (the debouncer is doing its job).
• generate for blinkers: all 4 LEDs blink at different rates from one module instantiation.
• Wrong widths: deliberately wire the 4-bit counter to drive 7-seg expecting 8 bits — find the warning in the Yosys log. That's a hardware bug caught at synthesis.

▸ Phase 5 of 5  ·  ~10 min

🔗 Transfer

Take it to the kitchen tonight

Tonight: Cooking Workshop = HDL Metaphor

Next: Catch-up Day → then Memory in Week 3