Today at a Glance

▸ Phase 1 of 5  ·  ~10 min

🌍 Contextualize

Storage is in everything you've touched in Barcelona

Memory Runs the City

▸ Phase 2 of 5  ·  ~15 min

⚠️ Reframe

Memory has physics. Code reflects it.

⚠️ Memory Is Not "Just an Array"

Synchronous vs. Asynchronous Read

The EBR Inference Pattern

module bram #(
    parameter ADDR_WIDTH = 8,
    parameter DATA_WIDTH = 8
)(
    input  wire                       clk,
    input  wire                       we,
    input  wire [ADDR_WIDTH-1:0]      addr,
    input  wire [DATA_WIDTH-1:0]      din,
    output reg  [DATA_WIDTH-1:0]      dout      // ← reg, registered
);
    reg [DATA_WIDTH-1:0] mem [0:(1<<ADDR_WIDTH)-1];

    always @(posedge clk) begin
        if (we) mem[addr] <= din;
        dout <= mem[addr];                       // ← READ inside @(posedge clk)
    end
endmodule

• dout is reg · the read is sequential · Yosys can map this to SB_RAM40_4K
• One always block for both ports — the standard "no read-during-write" pattern

⚠️ The Combinational-Read Trap

// ❌ This LOOKS efficient. It is not.
reg [7:0] mem [0:255];
assign dout = mem[addr];           // combinational read

always @(posedge clk)
    if (we) mem[addr] <= din;

// ✓ Synchronous read — Yosys can map to EBR
always @(posedge clk) begin
    if (we) mem[addr] <= din;
    dout <= mem[addr];
end

▸ Phase 3 of 5  ·  ~70 min  ·  You build

🛠 Assemble

ROM · RAM · TB · stretch

Build Plan

1. Ex 1 · 25 min  ROM-driven pattern sequencer — write a .hex, load with $readmemh, step a counter through addresses, drive LEDs & 7-seg.
2. Ex 2 · 25 min  Inferred Block RAM — 256×8 BRAM. Synthesize and confirm SB_RAM40_4K appears in yosys stat.
3. Ex 3 · 20 min  RAM testbench — read-after-write, overwrite, read from unwritten address.

ROM From a Hex File

module rom_seq #(
    parameter INIT_FILE = "patterns.hex"
)(
    input  wire       clk,
    input  wire [3:0] addr,
    output reg  [7:0] data
);
    reg [7:0] mem [0:15];

    initial $readmemh(INIT_FILE, mem);     // synthesizable in Yosys/iCE40

    always @(posedge clk) data <= mem[addr];   // registered read
endmodule

patterns.hex (one byte per line):

01
03
07
0F
1F
3F
7F
FF
...

Drive addr from a slow counter — LEDs trace the pattern at human speed.

RAM TB — Read-After-Write

// Self-checking pattern: write N, read back, verify
task automatic check (input [7:0] addr_i, input [7:0] data_i);
    begin
        @(posedge clk); we <= 1; addr <= addr_i; din <= data_i;
        @(posedge clk); we <= 0;                  // 1 cycle latency
        @(posedge clk);                            // capture
        if (dout !== data_i) begin
            $display("FAIL: wrote %02h at %02h, read %02h", data_i, addr_i, dout);
            fails = fails + 1;
        end
        tests = tests + 1;
    end
endtask

initial begin
    fails = 0; tests = 0;
    check(8'h00, 8'hA5);
    check(8'h01, 8'h5A);
    check(8'hFF, 8'hC3);
    check(8'h00, 8'h12);   // overwrite addr 0
    if (fails == 0) $display("PASS: %0d tests", tests);
    else            $display("FAIL: %0d/%0d", fails, tests);
    $finish;
end

Note the 2-cycle latency — write on edge 1, dout valid on edge 3. This is what "synchronous read" means.

▸ Phase 4 of 5  ·  ~45 min  ·  Confirm EBR · sweep · AI check

🛡 Fortify

Trust the synth report, not the source

Confirm Block RAM Inference

yosys -p "synth_ice40 -top bram; stat" bram.v 2>&1 \
    | grep -E "SB_RAM|SB_LUT4|SB_DFF"

SB_RAM40_4K  1
SB_LUT4      ~30
SB_DFF       ~8

SB_RAM40_4K  0
SB_LUT4      2048
SB_DFF       8

🤖 Check the Machine — BRAM Prompt

• Did the AI declare both dout outputs as reg? Many fall back to assign dout = mem[addr]; (combinational) — kills EBR inference.
• Does it use one always @(posedge clk) per port? The iCE40 EBR has two independently clocked ports.
• Does it instantiate SB_RAM40_4K directly? If so — politely refuse. We want inference, not hard instantiation. Inferred code is portable; the primitive isn't.
• Run yosys stat on the AI's code and your own. Compare. Save to portfolio.

Hardware Verification

• ROM sequencer: patterns from patterns.hex appear on LEDs / 7-seg at the expected cadence. Change the hex file, re-synth, see new pattern.
• BRAM: write a value via buttons, change address, write another, read back the first — both values survive. Persistence is the point.
• Wrong inference is invisible from the LED: the design still works with LUT RAM — it just costs 20× more area. yosys stat is the only honest check.

▸ Phase 5 of 5  ·  ~10 min  ·  Week 3 opens

🔗 Transfer

Where we left off, and where memory takes you

Where We Left Off — Weeks 1–2

Back from the catch-up day, free Friday, and weekend — here's the foundation memory builds on:

Tomorrow → D10 Timing & Numerical Architectures