Today at a Glance

▸ Phase 1 of 5  ·  ~10 min

🌍 Contextualize

A missed deadline is a safety stop

Timing Runs Barcelona

"My design works in simulation" is a sentence that ends a lot of internships. After today, you'll never trust a sim without a timing report.

▸ Phase 2 of 5  ·  ~15 min

⚠️ Reframe

Faster ≠ better. Critical path = boss.

⚠️ "Just Crank the Clock"

The Critical Path Owns Your Fmax

The PPA Triangle

What a + b Actually Builds

// One line of Verilog…
assign sum = a + b;

• …lets the synthesizer choose the architecture: ripple-carry, carry-lookahead, prefix-tree.
• On iCE40 Yosys picks ripple-carry — area-efficient, slow-ish Fmax — because the chip has fast carry chains.
• On a Xilinx 7-series, the same line might map to a DSP slice.
• The line is the spec. The hardware is the synth choice. You need both reports to know what you really built.

▸ Phase 3 of 5  ·  ~70 min  ·  You build

🛠 Assemble

Two adders · two multipliers · one Q4.4

Build Plan

1. Ex 1 · 30 min  Adder architecture comparison — ripple-carry (reuse D2 full_adder) vs behavioral +, at 8-bit and 16-bit. Record LUTs / FFs / Fmax for all 4 variants.
2. Ex 2 · 30 min  Shift-and-add multiplier — IDLE → COMPUTE → DONE FSM, accumulator + shift register. Then a behavioral *. Compare both.
3. Ex 3 · 20 min  Fixed-point Q4.4 — multiply two Q4.4 values, extract integer bits, drive 7-seg. Confirm 2.5 × 3.0 → 7 on display.

Adder Compare — The Setup

// Variant A — manual ripple-carry (reuse D2 full_adder)
module rca8 (input [7:0] a, b, input cin,
             output [7:0] sum, output cout);
    wire [7:0] c;
    full_adder fa0 (a[0], b[0], cin,  sum[0], c[0]);
    full_adder fa1 (a[1], b[1], c[0], sum[1], c[1]);
    // … chain c[1]→fa2, c[2]→fa3, …
    assign cout = c[7];
endmodule

// Variant B — behavioral
module add8 (input [7:0] a, b, output [8:0] sum);
    assign sum = a + b;          // tool chooses
endmodule

Synthesize both at 8 and 16 bits. The interesting question isn't which is smaller — it's whether they're the same circuit.

Shift-and-Add Multiplier (Skeleton)

module shift_add_mult #(parameter W = 8)(
    input  wire           clk, rst, start,
    input  wire [W-1:0]   a, b,
    output reg  [2*W-1:0] product,
    output reg            done
);
    typedef enum logic [1:0] {IDLE, COMPUTE, DONE} state_t;
    state_t state;
    reg [W-1:0]   mplier;
    reg [2*W-1:0] mcand;
    reg [3:0]     bit_idx;

    always @(posedge clk) begin
        if (rst) begin state <= IDLE; done <= 0; end
        else case (state)
            IDLE:    if (start) begin
                        product <= 0; mplier <= b; mcand <= a;
                        bit_idx <= 0; state <= COMPUTE;
                    end
            COMPUTE: begin
                        if (mplier[0]) product <= product + mcand;
                        mplier <= mplier >> 1;
                        mcand  <= mcand  << 1;
                        bit_idx <= bit_idx + 1;
                        if (bit_idx == W-1) state <= DONE;
                    end
            DONE:    begin done <= 1; state <= IDLE; end
        endcase
    end
endmodule

8 cycles per multiply. Trade: latency up 8×, area down ~5–10×.

Fixed-Point: Where the Bits Go

// Q4.4 × Q4.4 → Q8.8
wire [7:0]  a_q44, b_q44;       // 4 int . 4 frac
wire [15:0] prod_q88 = a_q44 * b_q44;

// Integer part for the 7-seg = bits [11:8] of Q8.8
wire [3:0]  int_part = prod_q88[11:8];

▸ Phase 4 of 5  ·  ~45 min  ·  Fill the table · believe the report

🛡 Fortify

No design ships without a PPA row

Read a nextpnr Timing Report

yosys -p "synth_ice40 -top add8; write_json add8.json" add8.v
nextpnr-ice40 --hx1k --json add8.json --pcf go_board.pcf \
              --asc add8.asc 2>&1 | tail -30

Info: Max frequency for clock 'i_Clk_$glb_clk':  78.43 MHz (PASS at 25.00 MHz)
Info: Critical path report:
Info: curr total
Info:  0.4  0.4  Source rca8.fa3.sum_$_DFFE_PP_/Q
Info:  2.1  2.5  Net rca8.fa3.sum to rca8.fa4.a
Info:  0.7  3.2  Source rca8.fa4.A → cout chain
…

• Fmax line is the headline — PASS / FAIL at your target.
• Critical path tells you where the slowest signal lives. That's where you'd pipeline.

Today's PPA Table

🤖 Check the Machine — Multiplier Prompt

• Did the AI write assign product = a * b;? Quick, wrong: that's the LUT-maximum version on iCE40. Push back.
• Did it write a sequential shift-and-add? Run yosys stat on both. Add the row to your PPA table.
• Did it claim a DSP slice? iCE40 HX1K doesn't have any. AI sometimes hallucinates Xilinx primitives. Reject and request iCE40-specific code.
• Save prompt + response + your correction to the AI portfolio. This is exactly the pattern Day 14 grades.

Hardware Verification

• Adder: drive a from switches, b from a counter, sum to LEDs. Watch the carry ripple at slow clock — that's the critical path you measured.
• Multiplier: press button → start. done LED pulses after 8 cycles. Result on 7-seg.
• Fixed-point: 2.5 × 3.0 → 7 on 7-seg. Try 1.5 × 2.0 → 3. Try 3.5 × 3.5 → 12 (with overflow into bit 12 — note the silent wrap).

▸ Phase 5 of 5  ·  ~10 min  ·  Toward UART · toward Metro

🔗 Transfer

Tomorrow your tools converge on one interface

Where This Goes