Today at a Glance

▸ Phase 1 of 5  ·  ~10 min

🌍 Contextualize

Every chip you've touched in Barcelona talks serial

Serial Is Everywhere

UART is 50 years old. It's the most-deployed protocol on Earth that isn't TCP/IP. You're learning the lingua franca.

▸ Phase 2 of 5  ·  ~15 min

⚠️ Reframe

There is no print(). There is a shift register.

⚠️ "Just Send a String"

The Four Blocks Inside "print"

The Frame on the Wire

  IDLE   START   D0   D1   D2   D3   D4   D5   D6   D7   STOP   IDLE
   1       0     b0   b1   b2   b3   b4   b5   b6   b7    1      1
  ─────┐  ┌──┐  ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐  ┌────────
       │  │  │  │  │ │  │ │  │ │  │ │  │ │  │ │  │ │  │  │
       └──┘  └──┘  └─┘  └─┘  └─┘  └─┘  └─┘  └─┘  └─┘  └──┘
                ◀──────────── 8 data bits, LSB first ────────────▶

• IDLE = line high. Always.
• START = 1 bit-period low. The falling edge is the receiver's only synchronization point — it sets the clock for the whole frame.
• DATA = 8 bits, LSB first. (This is the bug everyone hits at least once.)
• STOP = 1 bit-period high. Returns the line to idle.

Baud Math

// 25 MHz Go Board clock
// 115200 baud
parameter CLKS_PER_BIT = 25_000_000 / 115_200;
//                     = 217.01… ≈ 217

▸ Phase 3 of 5  ·  ~70 min  ·  You build

🛠 Assemble

Sim first · then "HELLO" on your laptop

Build Plan

1. Ex 1 · 40 min  UART TX in simulation — FSM (IDLE → START → DATA → STOP) + baud counter + bit counter. Testbench at CLKS_PER_BIT=4 for fast sim. Verify the 'A' (0x41) frame in GTKWave.
2. Ex 2 · 20 min  Single character on button — debounce (reuse D5 module), drive tx_data='A', pulse tx_start, route tx_out to the pin. Open terminal → see 'A'.
3. Ex 3 · 25 min  "HELLO\r\n" — 7-byte ROM + sequencer FSM that waits for tx_busy low before advancing.

The TX FSM — IDLE → START → DATA → STOP

UART TX (Skeleton)

module uart_tx #(parameter CLKS_PER_BIT = 217) (
    input  wire       clk, rst,
    input  wire       tx_start,
    input  wire [7:0] tx_data,
    output reg        tx_out,
    output reg        tx_busy
);
    localparam IDLE=3'd0, START=3'd1, DATA=3'd2, STOP=3'd3;
    reg [2:0]  state;
    reg [15:0] baud_cnt;
    reg [2:0]  bit_idx;
    reg [7:0]  data_latched;

    always @(posedge clk) begin
        if (rst) begin state <= IDLE; tx_out <= 1; tx_busy <= 0; end
        else case (state)
            IDLE:  begin tx_out <= 1; tx_busy <= 0;
                         if (tx_start) begin
                             data_latched <= tx_data; tx_busy <= 1;
                             baud_cnt <= 0; state <= START;
                         end end
            START: begin tx_out <= 0;                       // start bit
                         if (baud_cnt == CLKS_PER_BIT-1) begin
                             baud_cnt <= 0; bit_idx <= 0; state <= DATA;
                         end else baud_cnt <= baud_cnt + 1; end
            DATA:  begin tx_out <= data_latched[bit_idx];   // LSB first
                         if (baud_cnt == CLKS_PER_BIT-1) begin
                             baud_cnt <= 0;
                             if (bit_idx == 7) state <= STOP;
                             else              bit_idx <= bit_idx + 1;
                         end else baud_cnt <= baud_cnt + 1; end
            STOP:  begin tx_out <= 1;                       // stop bit
                         if (baud_cnt == CLKS_PER_BIT-1) state <= IDLE;
                         else baud_cnt <= baud_cnt + 1; end
        endcase
    end
endmodule

"HELLO" Sequencer

// 7-byte ROM in initial
reg [7:0] msg [0:6];
initial begin
    msg[0]="H"; msg[1]="E"; msg[2]="L";
    msg[3]="L"; msg[4]="O"; msg[5]="\r"; msg[6]="\n";
end

// Walk the ROM, wait for !tx_busy between bytes
always @(posedge clk) case (s)
    LOAD: begin tx_data <= msg[idx]; tx_start <= 1; s <= WAIT; end
    WAIT: begin tx_start <= 0;
                if (!tx_busy && tx_busy_d) begin           // falling edge
                    if (idx == 6) s <= DONE;
                    else begin idx <= idx + 1; s <= LOAD; end
                end end
endcase

▸ Phase 4 of 5  ·  ~45 min  ·  Sim · scope · AI

🛡 Fortify

If the terminal shows garbage, the bug is timing

Waveform vs Spec — Check Every Bit

• IDLE — line high for at least 1 cycle before tx_start.
• START — line low for exactly CLKS_PER_BIT cycles. Measure in the waveform.
• DATA bit 0 first — for 'A' = 0x41 = 0100_0001, the order on the wire is 1,0,0,0,0,0,1,0.
• STOP — line high for one full bit period. Then tx_busy drops.
• Total frame = 10 × CLKS_PER_BIT cycles, start to stop end.

🤖 Check the Machine — Protocol-Aware TB

• Did it measure bit duration? Many AI TBs just check value, not duration. A frame that's the right bits at the wrong rate is a fail in the real world.
• Did it check LSB-first? Watch for an MSB-first assumption — it'll silently "pass" wrong code.
• Did it test back-to-back TX? The tx_busy contract only matters when you push two bytes in a row.
• Annotate corrections, save to portfolio. This is the kind of protocol-aware testbench your project's verification builds on.

Hardware Verification

• Single char: button → 'A' on terminal. Hold the button — does it spam or pulse once? (Debouncer test.)
• "HELLO": press → "HELLO\r\n" appears. Press again — second copy appears on a new line. Now you have a printer.
• Scope/logic analyzer the TX line (if available) — measure 115.2 kHz bit rate directly. Confirm your math.
• Mismatch demo — set the terminal to 9600 baud. Same "HELLO" press. Watch the garbage. Now you've felt a baud mismatch in your bones.

▸ Phase 5 of 5  ·  ~10 min  ·  Park Güell · then build your project

🔗 Transfer

Protocols generalize. This afternoon: Gaudí's modular tiles.

Where This Goes