Today at a Glance

▸ Phase 1 of 5  ·  ~10 min

🌍 Contextualize

In industry, verification writes the spec

Assertions Are the Spec

An assertion that never fires might mean your design is correct — or that your TB never exercised that path. Coverage tells you which.

▸ Phase 2 of 5  ·  ~15 min

⚠️ Reframe

Assertions live inside the design

⚠️ "Testing Is the Last Step"

Immediate Assertions in 60 Seconds

always_ff @(posedge clk) begin
    // Contract: TX line idles high
    assert (state != IDLE || tx_out == 1'b1)
        else $error("TX low while IDLE at t=%0t", $time);

    // Contract: bit_idx in range during DATA state
    assert (state != DATA || bit_idx < 8)
        else $fatal("bit_idx overflow: %0d", bit_idx);

    // Contract: no new tx_start accepted while busy
    assert (!(tx_busy && tx_start))
        else $error("tx_start while busy — protocol violation");
end

• $error = sim continues, fail recorded. Good for non-fatal contract violations.
• $fatal = sim stops. Good for "we cannot continue — something is corrupt."
• Lives in the RTL file — code review sees them, regressions run them.

The Verification Maturity Ladder

▸ Phase 3 of 5  ·  ~70 min  ·  Contracts · parity · project TB

🛠 Assemble

Three deliverables · capstone Fortify

Build Plan

1. Ex 1 · 25 min  Assertion-enhanced UART TX — add ≥5 immediate assertions (idle high, busy semantics, bit-idx range, start=0/stop=1, no re-start while busy). Rerun TB; all pass.
2. Ex 2 · 20 min  Constraint-based parity (generate if) — PARITY_EN & PARITY_TYPE parameters. Conditionally insert a parity bit in the frame. Skippable if you're behind on your project.
3. Ex 3 · 25 min  🤖 AI constraint-based TB for your project module — write the constraint spec, prompt, audit, correct.

Bug Injection — Watch the Assertion Catch It

// Intentionally swap start/stop polarity
START: begin tx_out <= 1'b1;        // ❌ was 1'b0 — START should be LOW
             // …
       end

Re-run the existing TB. Assertion fires:

"START bit must be 0 at t=170 — got 1"
ASSERTION FAILED in uart_tx.sv:34
$finish called from sim — 1 error, 0 warnings

• Before assertions: you'd see garbage on the terminal and dig through 5000 cycles of waveform.
• With assertions: the message points to the exact line, the exact time, the exact violation. 2 seconds vs 20 minutes.
• Fix, re-run, watch all assertions pass. Commit the assertions to git, not just the fix.

Parity via generate if

module uart_tx_sv #(
    parameter int  CLKS_PER_BIT = 217,
    parameter bit  PARITY_EN    = 0,
    parameter bit  PARITY_TYPE  = 0      // 0=even, 1=odd
)(/* ports */);

    logic parity_bit;
    generate
        if (PARITY_EN) begin : gen_parity
            // Even parity: XOR reduction; flip if odd
            always_comb parity_bit = (^tx_data) ^ PARITY_TYPE;
            // FSM: IDLE → START → DATA(8) → PARITY → STOP
        end else begin : gen_no_parity
            assign parity_bit = 1'b0;    // unused, optimized away
            // FSM: IDLE → START → DATA(8) → STOP
        end
    endgenerate
endmodule

Compile two variants, run yosys stat on both. Question: how many LUTs does one parity bit cost?

🤖 AI Constraint-Based TB — The Capstone Prompt

• Does it actually constrain? Or does it generate fully random stimulus that misses corner cases?
• Does it self-check? A reference model in the TB compared to DUT output — that's the only way it scales.
• Does it count coverage? Manual bin counting is fine for now (covergroups need Verilator/commercial).
• Save to AI portfolio: spec + prompt + raw AI output + your corrected version + coverage analysis. This is the portfolio centerpiece.

▸ Phase 4 of 5  ·  ~45 min  ·  Coverage · PPA · structured report

🛡 Fortify

Numbers + paragraphs · the final-project rubric

How Do You Know When Testing Is Done?

• Assertions all pass — the contracts hold under every stimulus you ran.
• Coverage is closed — every important input combo + state was actually exercised. "Pass" without coverage is theater.
• The bugs you injected were caught — your TB sensitivity is non-zero.
• Code coverage ≥ X% — branch + toggle + FSM-state. Verilator can compute this; Icarus cannot.

The Capstone PPA Report

🤖 AI TB Critique — Did It Cover the Corners?

• Boundary values — did the TB hit 0, max, and max-1 for every input?
• Reset behavior — does the TB assert rst mid-operation and check recovery?
• Back-to-back operations — did it test the case that broke your "HELLO" sequencer yesterday?
• Illegal inputs — does the DUT handle them, and does the TB intentionally try?
• Coverage numbers — print them. If the AI didn't, add a manual counter and print it yourself.

▸ Phase 5 of 5  ·  ~10 min  ·  Where this fits

🔗 Transfer

From this room to silicon

How This Connects to the Required Course

Keep Going — Where to Take This Next

Try It On Your Own