Barcelona Abroad · Week 4 · Day 16🎤 Demo Day🤖 AI portfolio📊 PPA
Demos & Course Wrap
CRAFT cycle · 2.5 hours · Thu 6/18 · The deliverable is the day
HDL for Digital System Design · UCF ECE · Barcelona Summer 2026
CRAFT
Today at a Glance
Phase
Time
Activity
🌍 Contextualize
10 min
4 weeks ago vs now · the room reset
⚠️ Reframe
10 min
Demo = design review · trade-offs > results
🛠 Assemble
75 min
STUDENT DEMOS · 5 min live + 1 min Q&A · all cohort
🛡 Fortify
45 min
Peer feedback · AI portfolio share-out · retrospective
🔗 Transfer
10 min
Where you go next · UVM · formal · RISC-V · ASIC
Bulk of today (~120 min) is Assemble + Fortify. Demos = your "Assemble." Peer feedback + course retrospective = your "Fortify." This is the heaviest A+F balance of the week — by design.
▸ Phase 1 of 5 · ~10 min
🌍 Contextualize
Four weeks ago you blinked an LED
Where You Started · Where You Are
Day 1 · May 25
"What's a Verilog module?"
iCE40 toolchain on a fresh laptop
One blinking LED
"Why is hardware different from software?"
Day 16 · today
A multi-module synthesizable system
A self-checking testbench proving your core module
Industry context from 3 visits + a RISC-V architect
Same primitives the Metro · Semidynamics · HP · UAB use every day. Same toolchain. Different scale.
▸ Phase 2 of 5 · ~10 min
⚠️ Reframe
The demo is a design review · not a test
⚠️ "The Demo Is a Test"
❌ Student Frame
Show what works · hide what doesn't · pray the board cooperates · don't volunteer weaknesses.
✓ Engineer Frame
Show what works · explain what doesn't and what you'd do next · narrate your architectural trade-off · own your PPA · disclose what the AI got wrong and how you fixed it.
A well-understood partial project shows more learning than a black-box working one. The story is the deliverable.
The Demo Rubric (Reminder)
Segment
Time
What earns top marks
Context
1 min
One specific user / system / scenario · not "in general"
Live demo
1–2 min
The thing actually doing its job · backup video at the ready
Testbench
1 min
One waveform OR your self-checking TB catching a bug-injected variant
Trade-off
1 min
"I chose X over Y because [PPA / clarity / time]"
PPA + AI
30 s
LUTs · FFs · Fmax · the one AI TB correction you're proud of
Lessons
30 s
One surprise · one thing you'd change · ≤ 2 sentences
Strict 5-minute timer. At 4:30 a soft chime. At 5:00 hard stop. Q&A buffer is 1 min · time-boxed to keep the cohort moving.
▸ Phase 3 of 5 · ~75 min · The demos themselves
🛠 Assemble
12 demos · 5 min each · 1 min Q&A · random order
Logistics — Read Before You Start
Order: drawn from a hat at the start of phase. Pre-load nothing — be ready.
Setup: 60-second hand-off between demos. Practice plugging in fast — USB · power · serial monitor.
Visuals: if you have a slide, ONE slide on the projector while you talk. Code on the laptop, not the screen.
Backup: phone-video of your hardware working from last night. Show it ONLY if the live demo refuses to cooperate.
While others present: phones face-down. Notebook open. Write one specific question and one specific thing-they-did-better-than-you per demo.
Audience engagement is part of the demo grade. A silent cohort is a failing cohort.
Audience Notebook Template
## Demo Day · my notes · 6/18
### Demo 1 · <name> · <project>
- The trade-off they named:
- One thing they did better than I did:
- One specific question I'd ask if there were time:
### Demo 2 · …
### Demo 3 · …
### …
### Across all demos
- Best architectural choice I heard:
- Pattern I saw across multiple projects:
- AI workflow approach I'm stealing:
This file is the basis of your peer-feedback share-out in Fortify. Don't fake the entries — engaged audiences write better demos next time.
What Will Land Hard (Common Pitfalls)
"It just works" with no trade-off discussion → middle of the rubric.
Showing AI output verbatim without corrections → bottom of AI portfolio.
Skipping PPA ("I didn't have time") → fixable in 60 seconds with yosys stat; do it during someone else's demo if you have to.
Reading from slides → talk to the room. The slide is a prop.
Over-explaining what the code does → that's the README's job. The demo is for why.
If the board misbehaves mid-demo: keep talking. Diagnose out loud. That is the engineering skill on display — not the LED blinking.
▸ Phase 4 of 5 · ~45 min · Peer feedback · portfolio · retrospective
🛡 Fortify
Lock in the learning · close the loop
Peer Feedback Round (15 min)
Form groups of 3 (cycling through the cohort). Each person gets 3 minutes to receive feedback from the other two:
One concrete win — a specific architectural choice or explanation that worked
One concrete tweak — a specific change that would have made the demo stronger
One question you still have — something the demo opened up
Specific beats vague. "Good demo!" is not feedback. "Your trade-off slide on shift-add vs combinational mult was the clearest of the day" is feedback.
🤖 AI Portfolio Share-Out (15 min)
Each student: 90 seconds on the AI workflow they used. Round-robin, no slides.
What prompt did you write? Read it aloud (or paraphrase).
What did the AI generate that was wrong? Be specific. "Wrong reset polarity" lands; "it had bugs" doesn't.
How did you find the bug? This is the verification skill.
What would you trust the AI for next time? What wouldn't you?
This is the AI Workflow Portfolio (8% of grade) made tangible. Pattern-spotting across the cohort is half the value — write notes on others' approaches.
Course Retrospective (15 min · open mic)
Three rounds. Anyone can speak. Instructor stays silent the first round.
Round 1 · keep
One thing about the course that has to stay next cohort
Round 2 · cut
One thing that didn't earn its time
Round 3 · add
One thing missing — what would the perfect Week 5 cover?
Be specific. "More labs" → cut. "A second visit slot for HP debug bench" → useful. The feedback shapes next cohort's syllabus.
▸ Phase 5 of 5 · ~10 min · Where you go next
🔗 Transfer
The course closes · the practice begins
You Now Have These Things on Your CV
RTL fluency — Verilog · combinational + sequential · parameterized · hierarchical (SystemVerilog in the optional Keep Going track)
Verification discipline — manual TBs · self-checking · AI-scaffolded stimulus · coverage thinking (assertions & constrained-random in the optional track)
PPA intuition — yosys stat · nextpnr Fmax · area / freq / time-to-result trade-offs
FPGA deployment — open-source toolchain · bitstreams on real silicon · debugging across the abstraction stack
Industry context — Semidynamics (commercial RISC-V) · HP (verification at scale) · Metro (mission-critical embedded) · UAB (research)
AI workflow — prompt + audit + correct + document · not a black box, a tool
Where You Could Go Next
Path
Next step
Why it follows this course
UVM & commercial verif
UVM tutorial · class-based SV
Industry standard · Semidynamics / HP daily work
Formal verification
SymbiYosys · property suites
The path beyond simulation · catches bugs you can't see
✅ Final submission committed: code · constraints · TBs · AI portfolio · PPA · README
✅ Final reflection (≤ 500 words): "What I built · what I learned · what I'd do differently"
📅 Fri 6/19 — free / departure day · final reflection due 5pm
🌍 Keep building. The toolchain travels with you.
Stay in touch
The cohort channel stays open. Post your next FPGA project. Tag people whose demo gave you an idea. This is how engineering communities form.
🔗 Course closed · ¡gracias Barcelona!
You wrote modules. You shipped silicon. You're an HDL engineer now.
Four weeks. Three visits. One guest lecture. Twelve teaching days. One demo each. The path from hello_led to the next thing is shorter than you think — and now you know it.