Accelerated HDL for Digital System Design

Segment 1: Hardware Description Language Is Not Software

Topic 1, Video 1 of 4 · ~12 minutes

Dr. Mike Borowczak · Electrical & Computer Engineering · CECS · UCF

The Central Misconception

If you know C, Python, or Java, your instinct will be to read Verilog top-to-bottom and imagine it executing line by line.

This instinct is wrong.

Unlearning it is the single most important thing you'll do this week.

Software vs. Hardware

Software (C)

a = b + c;
d = a * 2;

Line 1 executes, completes,
then line 2 executes.

Hardware (Verilog)

assign a = b + c;
assign d = a * 2;

Both describe hardware that
exists simultaneously.

There is an adder. There is a shifter. They are both always active. When b changes, a and d both update — through physical gates.

Three Fundamental Differences

Concept	Software	Hardware (Verilog)
Execution	Sequential — one at a time	Concurrent — all at once
Assignment	"Compute and store"	"Create a permanent connection"
Time	Implicit — program counter	Explicit — propagation delay, clock edges

The River Analogy

Software as recipe vs Hardware as river system

Software (recipe) b=3, c=4

Course of execution	a	d
before line 1	—	—
after `a = b + c`	7	—
after `d = a * 2`	7	14

Hardware (river) inputs change over time

State of the river	a	d
steady^* (b=3, c=4)	7	14
steady^* (b=5, c=4)	9	18
steady^* (b=5, c=1)	6	12

^* after the river settles — see next slide

You are not writing instructions.
You are describing the geography of the river.

Here's an analogy that will carry you through the entire first week. Software is like following a recipe: do step 1, then step 2, then step 3. Sequential. Hardware is like a river system. Water flows through ALL tributaries simultaneously. If you add a dam here, it affects the flow over there. Everything is happening at once. Look at the two small tables. On the software side, there's a moment where a exists but d hasn't been computed yet — a real ordering. On the hardware side, a and d reflect the current inputs simultaneously — once the river has settled. Notice I said "steady" rather than "always." That asterisk matters. Concurrent does not mean instantaneous. The next slide unpacks that. [PAUSE — let this sink in] You are not writing instructions. You are describing the geography of the river. When you're confused about why Verilog behaves a certain way, come back to this analogy.

…But the River Takes Time to Flow

Concurrent does not mean instantaneous. When an input changes, the downstream water level doesn't snap to its new value — it settles.

Where the delay comes from:

Each gate has propagation delay (t_pd) — ns or ps.
Each wire adds delay too — charge has to redistribute.
Delays add up along a path (b → a → d).

What the table on the last slide showed:

The steady state — values after the river settles.
During settling, downstream signals are briefly stale or glitchy.
Truth tables describe steady state, not the transient.

Concurrent ≠ instantaneous. The river flows in parallel — but it still takes time.

Here's the nuance the previous slide hid behind the word "always." Concurrent does not mean instantaneous. When b changes, a doesn't update at the same instant. The adder gate has a propagation delay — a few nanoseconds for typical FPGA logic, picoseconds in modern ASICs. And d, which depends on a, can't settle until a has settled — so its delay is the adder delay plus the shifter delay. The yellow "in flight" regions are real. During those windows the downstream signal is briefly wrong or transitioning. Wires add delay too — moving charge through metal isn't free. So when we draw a truth table or write "a = 7 when b = 3 and c = 4," we mean the steady-state value, after the river has settled. The whole truth-table view of digital logic assumes you wait long enough between input changes for everything to settle. That's almost always a safe assumption in this course — but it is an assumption, and it's the foundation of everything we'll do with clocks in week three.

Why This Will Matter

For most of this week, “wait long enough for the river to settle” is implicit. But that settling time is what limits how fast a real chip can run.

The path determines the speed

The longest chain of gates between two storage elements (the critical path) sets the minimum clock period:

T_clk ≥ t_clk-to-Q + Σ t_pd + t_setup

More logic between flops → longer river → slower max clock.

For now, just remember:

Every gate adds a small delay.
Delays accumulate along a path.
Truth-table thinking = steady state.
Clocks (week 3) are how we make sure the river always has time to settle before sampling.

Foreshadow: When a synthesis tool reports “F_max = 161 MHz, slack = 33.8 ns,” it's measuring exactly this — how long the longest river takes to settle. We'll quantify it in Topic 10: Timing Essentials.

I don't want you to leave this video thinking delay is a footnote. It's the reason clocks exist. The longest chain of combinational logic between two flip-flops — what we call the critical path — sets your maximum clock frequency. The clock period has to be at least the clock-to-Q delay of the source flop, plus the sum of gate delays along the path, plus the setup time of the destination flop. More logic between flops means a longer river, which means a slower maximum clock. For week one, we'll mostly let this sit in the background — combinational logic settles, and we move on. But when you see synthesis reports later in the course saying things like "Fmax 161 megahertz, slack 33.8 nanoseconds," that's exactly what's being measured: how long the longest river takes to settle. We come back to this in detail on Topic 10.

More Code = More Hardware

Software

x = a + b;
y = c + d;

May reuse the same CPU adder at different times.

Verilog

assign x = a + b;
assign y = c + d;

Each implies its own physical adder. Two adders exist on the chip.

Resource awareness: More lines of Verilog = more gates = more FPGA resources consumed. You cannot malloc a flip-flop. Everything is fixed at synthesis time.

Parallelism Is Free

assign sum      = a + b;       // adder
assign product  = c * d;       // multiplier
assign result   = sum | product; // OR gate

All three operations happen at the same time.

No threads. No cores. No synchronization primitives.

In hardware, parallelism is the default. Sequentiality is what takes effort.

Software: sequential by default, parallel takes work.
Hardware: parallel by default, sequential takes work.

🤖 Check the Machine

Ask an AI assistant: “Here's a Verilog snippet with three assign statements on three lines. In what order do they execute?”

TASK

Paste three assign statements. Ask execution order.

BEFORE

Your prediction (now!): “Top to bottom, one at a time” — common wrong answer.

AFTER

Good AI models correctly say: all three are concurrent, no order. Weak models say “top to bottom.”

TAKEAWAY

If AI says “top to bottom,” it has the same bug you had. Use as a model-quality test.

Meta-lesson: This question is a litmus test. If an AI assistant tells you assign statements execute in file order, it's reasoning about Verilog as if it were C. Don't trust that AI for HDL work until you catch it making this mistake and correcting it.

Key Takeaways

① Verilog describes concurrent hardware, not sequential instructions.

② assign creates a permanent connection — a wire, not a variable.

③ More Verilog = more hardware. Resources are fixed at synthesis time.

④ Parallelism is free. Sequentiality takes effort.

You are describing the geography of the river — not writing a recipe.

Up Next

Synthesis vs. Simulation

Topic 1, Video 2 of 4 · ~10 minutes

The same Verilog file, two very different tools, two very different purposes.