Counter Variations

🌍 Where This Lives

⚠️ Two Kinds of Wraparound

📘 Modulo-N Counter — Definition

A modulo-N counter is a counter that takes values from $\{0, 1, 2, \ldots, N-1\}$ and wraps back to $0$ on the cycle after reaching $N-1$. It cycles forever through exactly $N$ distinct states.

Required width: to represent $N$ distinct values we need $$W \;=\; \lceil \log_2 N \rceil \;=\; \texttt{\$clog2}(N)$$ bits. The SystemVerilog primitive $clog2(N) computes the ceiling of the base-2 log at elaboration time — no off-by-one bugs.

Examples: $N{=}10 \Rightarrow W{=}4$ (since $2^4{=}16 \ge 10$); $N{=}1000 \Rightarrow W{=}10$; $N{=}500{,}000 \Rightarrow W{=}19$.

🔧 Modulo-N Counter — RTL View

👁️ I Do — Modulo-N Counter

module counter_mod_n #(parameter N = 10) (
    input  wire i_clk, i_reset, i_enable,
    output reg  [$clog2(N)-1:0] o_count,
    output wire o_wrap
);
    always @(posedge i_clk) begin
        if (i_reset)                          o_count <= 0;
        else if (i_enable && o_count == N-1) o_count <= 0;          // wrap
        else if (i_enable)                    o_count <= o_count + 1'b1;
    end
    assign o_wrap = i_enable && (o_count == N-1);                    // pulse at rollover
endmodule

🤝 We Do — Up/Down Counter

module up_down_counter #(parameter W = 8) (
    input  wire i_clk, i_reset, i_up,
    output reg  [W-1:0] o_count
);
    always @(posedge i_clk) begin
        if (i_reset)   o_count <= 0;
        else if (i_up) o_count <= o_count + 1'b1;
        else           o_count <= o_count - 1'b1;
    end
endmodule

🧪 You Do — Write the Loadable Counter

Extend the basic counter: synchronous load of i_load_val when i_load=1, otherwise increment.

Answer:

always @(posedge i_clk) begin
    if      (i_reset) o_count <= 0;
    else if (i_load)  o_count <= i_load_val;
    else              o_count <= o_count + 1'b1;
end

Priority: reset > load > count. This is the preload pattern used in timers and PWM period registers.

🎛️ Where Loadable Counters Live — A PWM Period Register

We've name-dropped “PWM period register” in a few decks now. Here's what one actually looks like — and why the loadable counter you just wrote is the period register.

🧩 PWM Period Register — RTL Sketch

Not the full peripheral — just the three pieces that turn the previous diagram into Verilog. The middle block is literally the loadable counter you just wrote, with the wrap event playing the role of i_load.

// 1) Period & duty registers — software-loadable (CSR-style)
reg [W-1:0] period, duty;          // period = N-1; duty = high-time
always @(posedge i_clk) begin
    if (i_we_period) period <= i_wdata;
    if (i_we_duty)   duty   <= i_wdata;
end

// 2) Period counter — same priority chain as the previous slide.
//    The "load" event is the natural end-of-period wrap.
reg [W-1:0] count;
always @(posedge i_clk) begin
    if      (i_reset)         count <= 0;
    else if (count == period) count <= 0;        // ← reload @ wrap
    else                      count <= count + 1'b1;
end

// 3) Duty comparator drives the PWM output
assign o_pwm = (count < duty);

🔧 What Did the Tool Build?

$ yosys -p "read_verilog day05_ex01_counter_mod_n.v; synth_ice40 -top counter_mod_n; stat" -q

=== counter_mod_n ===  (N=10, so width = $clog2(10) = 4 bits)
   Number of wires:                 14
   Number of cells:                 15
     SB_CARRY                        2     ← carry chain for +1
     SB_DFF                          0
     SB_DFFESR                       4     ← 4 counter flops
     SB_LUT4                         9     ← comparator logic + combinational

🤖 Check the Machine

Ask AI: “Write a parameterized Verilog counter that counts from 0 to N-1 and pulses a done signal at the end. Then estimate LUT count on an iCE40 for N=1000.”

Key Takeaways