Accelerated HDL for Digital System Design¶
UCF · College of Engineering & Computer Science · Department of ECE
A 4-week intensive course in Verilog and digital system design. Open-source toolchain, real FPGA hardware, AI-assisted verification.
🇪🇸 Barcelona Abroad Edition — Summer 2026¶
The full 16-day curriculum, adapted for a 4-week study-abroad format. 11 teaching sessions, 3 academic visits (Semidynamics · HP Barcelona · Metro Control Room), a guest RISC-V lecture, and the CRAFT pedagogical overlay (Contextualize → Reframe → Assemble → Fortify → Transfer) woven into every session.
Quick links
Cross-Cutting Threads¶
Weekly Arc¶
What Makes This Course Different¶
Real hardware, real toolchain, every session.
Learn to prompt, evaluate, and correct AI-generated testbenches.
Resource analysis via yosys stat becomes a habit, not a one-off exercise.
No license servers, no vendor lock-in — you keep the tools forever.
Toolchain Quick Reference¶
# Simulation (Icarus Verilog + GTKWave)
iverilog -o sim.vvp -g2012 tb_module.v module.v
vvp sim.vvp
gtkwave dump.vcd
# Synthesis & Programming (iCE40 open-source flow)
yosys -p "synth_ice40 -top top_module -json top.json" top.v
nextpnr-ice40 --hx1k --package vq100 --pcf go_board.pcf --json top.json --asc top.asc
icepack top.asc top.bin
iceprog top.bin