CRAFT Overlay — D11 — UART: Protocol Design & Implementation¶

Date: Wed 6/10 · (condensed: TX is the full lab; RX is covered conceptually + a stretch exercise — see Keep Going)

🌍 Contextualize¶

"Serial communication is everywhere — your Go Board's USB-to-UART bridge, the debug ports on the RISC-V chips at Semidynamics, the telemetry links in the Metro control room."

⚠️ Reframe¶

"If You're Thinking Like a Programmer: you send a string with print(). Reframe: You're building a state machine that shifts out one bit at a time at a precise baud rate. There's no print — there's a shift register, a baud counter, and an FSM."

🔑 Key Insight¶

"UART TX is an FSM that shifts bits out at a fixed rate. The protocol complexity is in the timing, not the logic."

🤖 Check the Machine¶

"Prompt AI for a protocol-aware UART testbench. Does it check baud timing precisely? Does it verify all 8 data bits? What about back-to-back transmissions? Annotate corrections."

🔗 Transfer¶

"You've designed a communication interface from the ground up — FSM, timing, verification. Tomorrow is a project build + lab catch-up day; then Week 4 takes you to the Metro control room (your skills at city scale), the project build day, the RISC-V guest lecture, and demos. Want more? UART RX, loopback, SPI, and SystemVerilog all live in the Keep Going self-study track."

Visit/Activity Connection¶

PM: Park Güell — Gaudí's modular tile system is parameterized design made physical: one repeating motif, varied across a surface — the same idea as the generate blocks and parameterized modules from D8.

Back to Barcelona Day Plan View Slides Baseline D11 Materials Baseline D12 Materials

This overlay supplements the baseline daily plan. All lab exercises and lecture content come from the baseline D11 + D12 materials.