HDL for Digital System Design — Barcelona Abroad Adaptation v2¶
Adaptation Overview¶
Baseline: 16-session curriculum (v2, with AI-assisted testbenches, PPA, numerical architectures) Barcelona schedule: 11 focused teaching sessions + 4 catch-up/build days + 1 guest lecture + 3 academic visits Pedagogical overlay: CRAFT cycle (Contextualize → Reframe → Assemble → Fortify → Transfer) infused into every session and enrichment activity Trimmed scope: SystemVerilog (design + verification) and other advanced material move to a guided self-study track — see Keep Going: Beyond the Scope of This Course.
What This Document Is¶
This is the abroad overlay — it maps the baseline curriculum onto the Barcelona calendar, identifies where content compresses, and specifies how CRAFT phases manifest in every session. The baseline course repo (hdl-for-dsd) remains the canonical source; this document drives the schedule and scaffolds the pedagogy.
Compression Strategy¶
The arc is trimmed and rebalanced: two baseline days are merged, UART is condensed, the two SystemVerilog days are removed, Memory is pushed from Week 2 into the room Week 3 opens up, and clocked logic (D4) shifts from the end of Week 1 into the start of Week 2 so Week 1 stays purely combinational and the sequential arc opens cleanly.
| Change | Rationale |
|---|---|
| D1+D2 → single session | Day 1 is dominated by toolchain setup and first board upload — in practice it leaves no time for a real lab. Merging it with D2 (data types, vectors, operators) makes Monday a setup-and-vocabulary session, with the combined lab finished during a Tuesday catch-up block. One Week-1 slot is reclaimed. |
| D5+D6 → single session | Testbenches verify the counters/shift registers just built — natural pairing. Students build a counter, then immediately write (and AI-generate) a testbench for it. The Fortify phase is built into the Assemble arc rather than living on its own day. |
| UART: 2 days → 1 day | UART TX is the core learning (baud timing, shift register, FSM-driven serialization). UART RX is structurally similar — oversampling and frame detection are covered in pre-class video + a stretch exercise, not a full lab day. Loopback becomes self-study. |
| SystemVerilog removed | The two SV days (design + verification) are cut from the required arc. SV is "Verilog with guardrails" — valuable, but not load-bearing for a first hands-on FPGA course. Both days move to the self-study track. The freed Week-3 slots become a project build/catch-up day and the landing spot for Memory. |
| Memory (D9) → Week 3 | Rather than dropping Memory, it moves out of a crowded Week 2 into Week 3, using the room the SV removal opens. Week 2 ends with a catch-up day instead. |
| Project rescoped | Reduced from 2 full build days + demo to 1 build day + demo. Project scope tightened to match. |
What's preserved: Week 1 combinational foundations (D1–D3), clocked logic (D4, now opening Week 2), FSMs (D7), Hierarchy/Parameters (D8), Memory (D9), Timing/Numerical Architectures (D10), and UART TX (D11).
What moves to self-study: SystemVerilog for Design, SystemVerilog for Verification, UART RX/loopback, SPI, and the three highest-complexity project options — all collected under Keep Going.
CRAFT Session Template¶
Every 2.5-hour teaching session follows this structure:
┌─────────────────────────────────────────────────────┐
│ 🌍 CONTEXTUALIZE (10 min) │
│ "Where This Lives" opener — real-world framing │
│ Connect to academic visit / Barcelona context │
├─────────────────────────────────────────────────────┤
│ ⚠️ REFRAME (15 min) │
│ Mini-lecture: surface the misconception, install │
│ the correct mental model. │
│ "If You're Thinking Like a [X]..." moment │
│ ❓ "No Dumb Questions" pause before lab │
├─────────────────────────────────────────────────────┤
│ 👁️🤝🧪 ASSEMBLE (80–90 min) │
│ 👁️ I Do: Instructor live-codes the concept (15) │
│ 🤝 We Do: Guided exercise, students follow (25) │
│ 🧪 You Do: Independent lab exercises (40–50) │
│ 💡 Pattern named when first introduced │
│ 🔑 Key Insight captured on board/slide │
├─────────────────────────────────────────────────────┤
│ 🔧🤖 FORTIFY (20 min) │
│ 🔧 "What Did the Tool Build?" — synthesis/sim │
│ 🤖 "Check the Machine" — AI verification exercise │
│ 🧠 "How You Learn" metacognitive moment │
├─────────────────────────────────────────────────────┤
│ 🔗 TRANSFER (10 min) │
│ "What's Next" — bridge to tomorrow's content │
│ 📊 Industry Alignment connection │
│ Homework + pre-class video assignment │
└─────────────────────────────────────────────────────┘
Full Calendar Mapping¶
Week 1: Verilog Foundations (May 25–29)¶
| Date | Cal Day | Baseline | Barcelona Session | Key CRAFT Moments |
|---|---|---|---|---|
| Mon 5/25 | CLASS (merged) | D1+D2 | Hardware Thinking + Data Types, Vectors & Operators | 🌍 "You're learning HDL in a city built by Gaudí — an architect who thought in parallel structures and modular repetition." ⚠️ "Variables are storage → wires are physical connections that exist simultaneously." Setup + first board upload + data-type vocabulary in one session. |
| Tue 5/26 | CATCH-UP | — | Setup completion + combined D1+D2 lab finish | 🧪 Buffer: students who lost Monday to toolchain issues finish board bring-up; everyone completes the combined combinational/data-type lab. Light, instructor-supported. |
| Wed 5/27 | CLASS | D3 | Combinational Logic & always@(*) | 🔧 Yosys schematic: see if/else vs case synthesis side-by-side. PM: Sagrada Familia |
| Thu 5/28 | EXCURSION | — | Montserrat Day Trip | 🌍 Informal: parallel mountain paths ≈ parallel hardware; funicular = state machine |
| Fri 5/29 | CATCH-UP | — | Combinational lab catch-up + Week 2 prep | 🧪 Buffer: finish the combinational labs (D3) and pre-load the D4 clocked-logic video before the weekend. D4 has moved to Week 2 so Week 1 stays purely combinational. |
Notes: D1 and D2 merge into Monday because Day 1 is realistically all setup and the first board upload. Tuesday is a catch-up block to absorb setup overruns and finish the combined lab. D3 (Wed) is paired with Sagrada Familia and Montserrat falls on Thursday. D4 (clocked logic) has moved out of Week 1 into Week 2 — it is sequential content and belongs with the sequential-design arc, so Week 1 now closes with a Friday catch-up/prep block and contains only combinational foundations.
Week 2: Sequential Design, Verification & Structure (Jun 1–5)¶
| Date | Cal Day | Baseline | Barcelona Session | Key CRAFT Moments |
|---|---|---|---|---|
| Mon 6/1 | CLASS | D4 | Clocked Logic & RTL Thinking | 🌍 "The flip-flops and clocked registers you build today are the pipeline registers inside every RISC-V core — you'll see Semidynamics' processors this afternoon." 🤖 First "Check the Machine": ask AI to explain blocking vs. nonblocking — verify against what you just learned. PM: Semidynamics visit |
| Tue 6/2 | CLASS | D5+D6 | Counters, Testbenches & AI Verification | 🤖 Build-then-verify arc: counter → testbench → AI testbench. ⚠️ "If it simulates, it works" → simulation proves correctness for tested cases only. |
| Wed 6/3 | CLASS | D7 | Finite State Machines | ⚠️ "If You're Thinking Like a Programmer: FSM = switch in a loop. Reframe: FSM = physical flip-flops + combinational next-state logic." Eve: Cooking workshop (recipe = a sequence of states = an FSM) |
| Thu 6/4 | CLASS | D8 | Hierarchy, Parameters & Generate | 🔧 Parameterize a module, synth at 3 widths, compare yosys stat. PM: HP visit (parameterized, reusable IP + verification at industrial scale) |
| Fri 6/5 | CATCH-UP | — | Lab catch-up + Week 3 prep | 🧪 Reserved for finishing the week's labs and scoping a project. Memory (D9) moves to Week 3, so Week 2 still closes with a buffer day even though D4 now opens it. |
D5+D6 Merge — CRAFT Overlay:
- 🌍 Contextualize: Counters and shift registers are inside every timer, serial link, and pipeline — and a testbench is how you earn the right to trust them
- ⚠️ Reframe: Bounce needs a saturating counter, not
delay(); simulation ≠ proof of correctness - 🔑 Key Insight: A testbench is not optional — writing it before the design is better
- 🤖 Check the Machine: AI-generate a TB for debounce; compare coverage against manual TB
- 🔗 Transfer: Sequential + verification mastered → FSMs tomorrow
See craft/day05_day06_craft.md for full CRAFT overlay.
Pre-class video: D4's clocked-logic video (V4, 50 min) is watched over the Sat/Sun weekend ahead of Monday. The D5 video (counters/debounce, 45 min) and D6 video (testbench anatomy, 55 min) are then split across Sunday and Monday evening ahead of Tuesday's merged session. Total D5+D6: ~100 min.
Week 3: Memory, Timing & Communication (Jun 8–12)¶
| Date | Cal Day | Baseline | Barcelona Session | Key CRAFT Moments |
|---|---|---|---|---|
| Mon 6/8 | CLASS | D9 | Memory: RAM, ROM & Block RAM (moved from Week 2) | 🔑 "Memory has physical constraints: read latency, port count, initialization. Coding patterns determine whether Yosys infers EBR or LUTs." |
| Tue 6/9 | CLASS | D10 | Timing, Numerical Architectures & PPA | 🌍 "Every interface you'll build depends on timing. The Barcelona Metro runs on precisely timed digital control — you'll see that control room next week." Project selection due. Eve: Flamenco |
| Wed 6/10 | CONDENSED | D11 | UART: Protocol Design & Implementation | 👁️🤝🧪 Full Assemble arc for TX; RX covered conceptually + stretch exercise. PM: Park Güell |
| Thu 6/11 | PROJECT | — | Project build + lab catch-up | 🧪 Structured project work + lab catch-up. This is one of the two slots freed by removing the SystemVerilog days. |
| Fri 6/12 | FREE | — | Independent project work |
SystemVerilog removed from Week 3. The two SV days (design + verification) that previously sat Wed/Thu are cut from the required arc and moved to the self-study track. The freed room lets Memory (D9) move here from Week 2 and opens a dedicated project build/catch-up day (Thu 6/11).
UART Condensed — What Stays, What Goes:
| Content | Status | Rationale |
|---|---|---|
| UART protocol fundamentals (framing, baud, start/stop) | ✅ Stays — in pre-class video + mini-lecture | Essential context |
| UART TX design & implementation | ✅ Stays — full I Do → We Do → You Do | Core learning: FSM-driven serialization, baud timing |
| UART TX testbench (AI-assisted) | ✅ Stays — Fortify exercise | Reinforces AI verification thread |
| UART TX deployment to Go Board | ✅ Stays — HW verification | Students see their bytes on a terminal |
| UART RX (16× oversampling, frame detection) | 📹 Pre-class video only | Conceptually important but structurally similar to TX |
| UART RX implementation lab | ⬇️ Stretch exercise | Available for fast students; not required |
| UART loopback (TX→RX echo) | ❌ Dropped from required | Cool demo but not essential for learning objectives |
| SPI Master | ❌ Dropped | Was already a stretch exercise; out of scope for abroad |
Condensed UART — CRAFT Overlay:
- 🌍 Contextualize: Serial communication everywhere — Go Board USB-UART, Semidynamics debug ports, Metro telemetry
- ⚠️ Reframe:
print()→ FSM that shifts bits at a precise baud rate; noprint, just shift register + counter + FSM - 🔑 Key Insight: UART TX = FSM shifting bits at a fixed rate; complexity is in timing, not logic
- 🤖 Check the Machine: AI protocol-aware UART TB — does it check baud timing, all 8 data bits, back-to-back TX?
- 🔗 Transfer: Communication interface from scratch → SystemVerilog tomorrow
See craft/day11_craft.md for full CRAFT overlay.
Week 4: Integration, Transfer & Demonstration (Jun 15–19)¶
| Date | Cal Day | Baseline | Barcelona Session | Key CRAFT Moments |
|---|---|---|---|---|
| Mon 6/15 | VISIT | — | Barcelona Metro Control Room (10 AM) | 🌍 Capstone Contextualize: FSMs, serial buses, memory, timing — running a city's transit |
| Tue 6/16 | CLASS | D15 | Project Build Day | 🧪 All You Do: structured project work + PPA analysis + AI-assisted final TB |
| Wed 6/17 | GUEST | — | RISC-V Lecture (David Castells Rufas, UAB) | 🌍🔗 Capstone Transfer: from your first module to processor design |
| Thu 6/18 | CLASS | D16 | Project Demos & Course Wrap | 🔗 "Where to go from here" — ASIC/FPGA careers, UVM, formal verification |
| Fri 6/19 | FREE | — | Departure / free day |
Rescoped Final Project¶
Why Rescope¶
The baseline project assumed 2 full build days (D15–D16 with demo on D16 afternoon). The Barcelona schedule provides 1 build day (Tue 6/16) + demo (Thu 6/18), with independent work time on evenings and the Wed 6/17 afternoon. Students have comparable total project time but less structured class time.
Revised Project Parameters¶
| Parameter | Baseline | Barcelona |
|---|---|---|
| Build days in class | 2 (D15 full + D16 morning) | 1 (D16 full) |
| Demo format | 10-min presentation + live demo | 5-min live demo + 2-min Q&A |
| Core deliverables | Working demo + code + testbenches + PPA report + AI portfolio | Working demo + code + 1 testbench + brief PPA snapshot |
| Scope | Full project from 9-option list | Reduced project from 6-option list (3 highest-complexity options removed) |
Revised Project Options (6 options, complexity-capped)¶
| # | Project | Key Concepts | Difficulty | Removed? |
|---|---|---|---|---|
| 1 | UART Command Parser | FSM + UART TX + string matching + LED control | ★★ | |
| 2 | Digital Clock / Timer | Counters + 7-seg multiplexing + button FSM | ★★ | |
| 3 | Pattern Generator | Shift registers + LFSR + LED sequencing + parameterization | ★☆ | |
| 4 | Reaction Time Game | FSM + counter + random delay + 7-seg display | ★★ | |
| 5 | Tone Generator | Counter-based frequency synthesis + button UI + 7-seg | ★★ | |
| 6 | Conway's Game of Life | Memory + neighbor logic + VGA/LED display + FSM | ★★ | |
| — | ~~SPI Sensor Interface~~ | ~~SPI master + FSM + data parsing~~ | ~~★★★~~ | ❌ Requires SPI (dropped) |
| — | ~~VGA Pattern Display~~ | ~~Timing-critical VGA + frame buffer~~ | ~~★★★~~ | ❌ Too much timing work for schedule |
| — | ~~Simple Processor~~ | ~~ALU + register file + FSM sequencer~~ | ~~★★★~~ | ❌ Scope too large; RISC-V lecture covers conceptually |
Revised Project Deliverables¶
Each project requires:
- Working hardware demo (5 min) — deployed on Go Board, demonstrated live
- Source code — clean, commented, following course conventions (
r_/w_/i_/o_prefixes, parameterized where appropriate) - One self-checking testbench — for the core module (FSM, counter, or data path). May be manually written or AI-generated-then-corrected.
- PPA snapshot —
yosys statoutput for the top-level module: LUT count, FF count, % iCE40 utilization. Two sentences on what's using the most resources and why. - AI interaction log — one example of AI-assisted testbench or code generation with annotations: what you prompted, what it produced, what you corrected.
Revised Project Timeline¶
| Date | Milestone |
|---|---|
| Tue 6/9 (Week 3, D10) | Project selection due — choose from 6 options or propose custom (approved by instructor) |
| Wed 6/10 (Week 3, D11) | Block diagram and module list submitted (1-page sketch) |
| Thu 6/11 (end of Week 3) | Core module implemented — at least the primary FSM or data path compiles and simulates. Testbench started. |
| Fri 6/12 – Mon 6/15 | Independent work time (weekend + Metro visit day afternoon) |
| Tue 6/16 | Build day — integration, debugging, PPA analysis, AI-assisted TB polish |
| Wed 6/17 afternoon | Independent polish time (after RISC-V lecture) |
| Thu 6/18 | Demo day — 5-min demos, all deliverables due by end of day |
Revised Project Grading¶
| Component | Weight | Notes |
|---|---|---|
| Working hardware demo | 35% | Does it work? Does it match the spec? |
| Code quality | 20% | Conventions, parameterization, readability |
| Testbench + verification | 20% | Self-checking, covers core functionality |
| PPA snapshot + AI log | 15% | Shows synthesis awareness + AI literacy |
| Live demo presentation | 10% | Clear explanation, handles Q&A |
Academic Visit Integration¶
Semidynamics (Mon 6/1, 4:00–5:30 PM)¶
Pre-visit framing (end of morning class):
"Semidynamics designs RISC-V processors. The flip-flops and clocked registers you wired up today are the pipeline registers at the heart of what they ship. As you tour: How do they verify their designs? What's their relationship between simulation and silicon?"
Post-visit reflection (start of Tue class, 5 min):
"What surprised you? → bridges into counters & verification: "The pipelined datapaths they described are built from registers and counters — today you build and verify those sequential blocks."
HP Customer Center (Thu 6/4, afternoon)¶
Pre-visit framing (end of D8 morning class):
"Today you parameterized a module so one design scales to any width — that's how companies ship reusable IP. HP builds and verifies hardware at exactly that scale, and uses AI to do it (just like the AI testbenches you wrote earlier this week). As you tour: how do they manage and verify designs across whole product families?"
Post-visit reflection (start of Fri catch-up, 5 min):
"HP showed reusable IP, verification, and AI tooling at industrial scale. Today you commit to a project — think about which parts you'll parameterize and how you'll verify them."
Barcelona Metro Control Room (Mon 6/15, 10 AM)¶
Pre-visit prep (assigned end of Thu 6/11):
"The Metro's automated lines run on digital control systems. As you tour: Where are the FSMs? Where is serial communication happening? Where is memory being used? Write down 3 observations connecting what you see to what you've built."
Post-visit debrief (start of Tue 6/16, 10 min):
Student share-out → transitions into project build day. "Everything you saw yesterday — you have the skills to build the components of those systems."
David Castells Rufas RISC-V Lecture (Wed 6/17, 10 AM)¶
Pre-lecture prep (assigned end of Tue 6/16):
"David designs RISC-V processors in the same HDL you've been writing. Come with 2 questions about how your course concepts apply to processor design."
Role in CRAFT arc: This is the course's capstone 🌍 Contextualize + 🔗 Transfer moment. "You now have the foundation to understand and contribute to what David does."
CRAFT Threads Across the Full Course¶
🌍 Contextualize — "Where This Lives"¶
| Session | Anchor |
|---|---|
| D1+2 (Mon 5/25) | Gaudí's Barcelona — parallel structures, modular design; binary in everything (phone, metro reader, airport scanner) |
| D3 (Wed 5/27) | Real-time decisions → Sagrada Familia: structural calculations |
| D4 (Mon 6/1) | Clocked registers & flip-flops → Semidynamics RISC-V pipeline registers that afternoon |
| D5+6 (Tue 6/2) | Counters/shift registers in every timer and pipeline; a testbench is how you trust sequential logic |
| D7 (Wed 6/3) | FSMs control vending machines, train doors; a recipe is an FSM → Cooking workshop that evening |
| D8 (Thu 6/4) | Parameterized, reusable IP = how companies build products at scale → HP that afternoon |
| D9 (Mon 6/8) | Memory in every system: cache, frame buffers, lookup tables |
| D10 (Tue 6/9) | Timing is what makes hardware hard; Metro timing next week |
| D11 (Wed 6/10) | Serial protocols: same UART on your Go Board's USB bridge |
| Metro (Mon 6/15) | 🌍 Capstone: Digital systems running a city |
| Build (Tue 6/16) | Your project = same development cycle professionals follow |
| RISC-V (Wed 6/17) | 🔗 Capstone Transfer: From first module to processor design |
| Demo (Thu 6/18) | You are an HDL designer. Where does this take you? |
⚠️ Reframe — "If You're Thinking Like a..."¶
| Session | Misconception → Correct Model |
|---|---|
| D1+2 | "HDL is a programming language" → "HDL describes physical hardware that runs in parallel" / "Variables store values" → "Wires are connections; reg is storage, not a variable" |
| D3 | "if/else is like C" → "Priority-encoded mux chains vs. parallel muxes — different HW cost" |
| D4 | "Code executes top to bottom" → "Everything in always describes what happens on a clock edge — simultaneously" |
| D5+6 | "Buttons just work" → "Mechanical contacts bounce; you need a saturating counter" / "If it simulates, it works" → "Simulation proves correctness for tested cases only" |
| D7 | "FSM = switch in a loop" → "FSM = flip-flops + combinational logic; 3-block separates concerns" |
| D8 | "Copy-paste is reuse" → "Parameters + generate create hardware at elaboration, not runtime" |
| D9 | "Memory is just an array" → "Physical constraints: latency, ports, init. Coding patterns → EBR inference" |
| D10 | "Faster clock = better" → "Timing closure means every path must meet setup/hold" |
| D11 | "Serial is slow" → "Serial saves pins. 115200 baud = 11.5 KB/s — enough for embedded control" |
👁️🤝🧪 Assemble — Key I Do → We Do → You Do Arcs¶
| Session | I Do | We Do | You Do |
|---|---|---|---|
| D1+2 | Live-code hello_led |
Modify blink pattern | Design 4-LED binary counter |
| D3 | Build mux, show synthesis | Build 7-seg decoder together | Priority encoder + ALU |
| D5+6 | Counter + TB | Add LFSR + AI TB together | Mod-N counter + TB comparison |
| D7 | Traffic light FSM | Add pedestrian button | Pattern detector or vending FSM |
| D9 | ROM lookup table | RAM read/write together | Memory-backed pattern sequencer |
| D11 | UART TX live build | Add baud parameter together | Deploy — send your name to terminal |
🔧🤖 Fortify — Tool + AI Verification Progression¶
| Session | 🔧 Tool Verification | 🤖 AI Verification |
|---|---|---|
| D3 | Yosys schematic: if/else vs case |
— |
| D4 | GTKWave: clock edge behavior | Ask AI to explain blocking vs. nonblocking |
| D5+6 | GTKWave: manual vs AI waveforms | First AI TB generation + comparison |
| D8 | yosys stat at multiple widths (PPA) |
AI TB for parameterized counter |
| D9 | EBR inference check in synthesis report | AI-generated memory test patterns |
| D11 | PPA: UART at 9600 vs 115200 | AI protocol-aware UART TB |
| Build Day | PPA snapshot for final project | AI-assisted final TB with corrections |
🔗 Transfer — "What's Next" Bridges¶
| Session | Bridge |
|---|---|
| D4 → D5+6 | "You can build anything on a clock edge. Tomorrow: useful sequential circuits + how to verify them." |
| D5+6 → D7 | "You can build and verify sequential blocks. Tomorrow: FSMs tie everything together." |
| D8 → D9 | "You build reusable, parameterized blocks. After the catch-up day and weekend, Week 3 opens with memory — where your data lives." |
| D10 → D11 | "Timing is what makes interfaces work. Tomorrow: UART — your first communication protocol, built from FSM + counter + shift register." |
| D11 → Project | "You built a communication interface from scratch. Tomorrow is a project build/catch-up day — then Week 4: see your skills at city scale (Metro), then build and demo your own design." |
| RISC-V → Demo | "David showed where HDL skills lead. Tomorrow: you demonstrate yours." |
Standing CRAFT Elements — Per Session Checklist¶
| Element | Manifestation | When |
|---|---|---|
| 🔑 Key Insight | Written on board at the moment it lands; students photograph | During Reframe or Assemble |
| 📊 Industry Alignment | Explicit professional connection — amplified by visits | During Contextualize |
| ❓ No Dumb Questions | 3-min pause: "What question are you embarrassed to ask?" | After Reframe, before Assemble |
| 💡 Pattern | Named and catalogued (e.g., "3-block FSM," "parameterized counter") | During I Do |
| 📜 Legacy Alert | Verilog-95 vs -2001 vs SV when it matters | As encountered |
| 🧠 How You Learn | Metacognitive moment: "What changed in your mental model today?" | End of Assemble, before Fortify |
| 🤖 Check the Machine | AI exercise — minimum one per session from D4 onward | During Fortify |
Pre-Class Video Schedule¶
| Barcelona Session | Pre-Class Video(s) | Watch Time | Assigned |
|---|---|---|---|
| D1+D2 (Mon 5/25) | V1 + V2 (HDL Mindset + Data Types & Operators) | 85 min | Before arrival (online) |
| D3 (Wed 5/27) | V3: Combinational Logic | 45 min | Tue evening |
| D4 (Mon 6/1) | V4: Clocked Logic | 50 min | Over Sat/Sun weekend |
| D5+6 (Tue 6/2) | V5 + V6 | 100 min | Split Sun + Mon evening |
| D7 (Wed 6/3) | V7: FSMs | 50 min | Tue evening |
| D8 (Thu 6/4) | V8: Hierarchy & Parameters | 50 min | Wed evening |
| D9 (Mon 6/8) | V9: Memory | 45 min | Over Fri–Sun weekend |
| D10 (Tue 6/9) | V10: Timing & Numerical Architectures | 55 min | Mon evening |
| D11 (Wed 6/10) | V11 + V12 (TX focus + RX conceptual) | 90 min | Split Mon + Tue evening |
| Build (Tue 6/16) | None — project work | — | — |
| Demo (Thu 6/18) | None | — | — |
Total required pre-class video: ~570 min (~9.5 hrs) — down from the baseline ~710 min. The SV videos (V13 SV Design, V14 SV Verification) are retained as optional resources in the self-study track.
Assessment¶
Grading emphasizes hands-on lab and technical work (~85%) while recognizing engagement and enrichment activities (~15%).
Labs & Technical Work (85%)¶
| Component | Weight | Notes |
|---|---|---|
| Lab exercises (9 sessions) | 72% | 8% per lab; 9 graded lab sets (D1+2, D3, D4, D5+6, D7, D8, D9, D10, D11) |
| Final project | 5% | Lightweight capstone demo |
| AI workflow portfolio | 8% | AI TB generations + corrections + reflections |
Activities & Engagement (15%)¶
| Component | Weight | Notes |
|---|---|---|
| Visit reflections | 10% | 3 CRAFT-aligned write-ups (Semidynamics, HP, Metro) |
| Participation & engagement | 5% | In-class contributions, questions, peer collaboration |
Academic Visit Reflection Format (CRAFT-aligned, 1 page max):
- 🌍 What did you see? — Describe the technology or system
- ⚠️ What surprised you? — What contradicted your expectations?
- 🔧 What connects? — Which course concepts did you recognize?
- 🔗 What's next? — How does this shift your thinking about your project or career?
Cultural Activities as Informal CRAFT Touchpoints¶
Not graded, not forced — just seeds for organic conversation:
| Activity | Possible Connection |
|---|---|
| Sagrada Familia (Wed 5/27) | Parallel construction, modular repetition, systems thinking |
| Montserrat (Thu 5/28) | Funicular = state machine with safety interlocks |
| Cooking Workshop (Wed 6/3) | Recipe = sequential; kitchen with multiple cooks = parallel |
| Flamenco (Tue 6/9) | Rhythm structures (palos) = clock domains; improvisation within constraints |
| Park Güell (Wed 6/10) | Modular tile system = parameterized design; repeating with variation = generate |
Summary: Baseline → Barcelona¶
| Dimension | Preserved | Merged / Compressed | Moved to Self-Study | New |
|---|---|---|---|---|
| D1 hardware thinking + D2 data types | ✅ Merged → 1 session (+ Tue catch-up) | |||
| D3 combinational foundations (Week 1) | ✅ | |||
| D4 clocked logic (moved to open Week 2) | ✅ | |||
| D5 counters + D6 testbenches | ✅ Merged → 1 session | |||
| D7 FSMs | ✅ | |||
| D8 hierarchy/params | ✅ | |||
| D9 memory | ✅ (moved to Week 3) | |||
| D10 timing/numerical | ✅ | |||
| D11 UART TX | ✅ | |||
| UART RX + loopback | 🔜 RX/loopback → self-study | |||
| SPI Master | 🔜 Self-study | |||
| SV Design (baseline D13) | 🔜 Self-study | |||
| SV Verification (baseline D14) | 🔜 Self-study | |||
| D15+D16 Project | ✅ 1 build + 1 demo | |||
| 3 highest-complexity projects | 🔜 Self-study | |||
| Project build/catch-up days | ✅ Tue 5/26, Fri 5/29, Fri 6/5, Thu 6/11 | |||
| Academic visits | ✅ 3 visits | |||
| Guest lecture | ✅ RISC-V | |||
| CRAFT session template | ✅ Every session | |||
| Visit reflections | ✅ Assessment |
Keep Going: Beyond the Scope of This Course¶
The Barcelona edition deliberately trims scope so the in-person hours stay focused and humane. Nothing below is cut from the discipline — it's lifted out of the required schedule and gathered here as a guided self-study track. Each item points at the baseline course materials that already exist in this repo, so a motivated student can keep going on their own (or in a follow-on course). None of it is graded in the abroad edition.
Why these moved out¶
Day 1 in practice is entirely toolchain setup and the first board upload, so D1 and D2 were merged and a Tuesday catch-up block added. With Day 1+2 and Day 5+6 merged and the project rescoped to a single build day, the SystemVerilog days were the natural next trim: SV is "Verilog with guardrails" — genuinely useful, but not load-bearing for a first hands-on FPGA build. Removing both SV days opened the Week-3 room that lets Memory (D9) relocate there and creates a dedicated project build/catch-up day.
The self-study track¶
| Topic | What it covers | Where to start | Prereqs |
|---|---|---|---|
| SystemVerilog for Design | logic (one type for wire+reg), always_ff / always_comb / always_latch intent declarations, enum typed states, typedef, packed struct. Refactor a Verilog FSM to SV and let the tool catch latch/intent mistakes. |
Baseline D13 daily plan · CRAFT overlay: D12 — SV for Design · optional video V13 | D7 FSMs, D8 hierarchy |
| SystemVerilog for Verification | Assertions (SVA) as executable specs, functional coverage, constraint-random stimulus, and a first look at UVM concepts. AI constraint-based testbench for your project module. | Baseline D14 daily plan · CRAFT overlay: D13 — SV for Verification · optional video V14 | D5+6 testbenches, D11 UART |
| UART RX | 16× oversampling, start-bit detection, mid-bit sampling, frame assembly. Structurally similar to TX — the natural next build after the TX lab. | Baseline D12 daily plan (RX & SPI) · video V12 (RX conceptual, already assigned) | D11 UART TX |
| UART Loopback | TX→RX echo on the Go Board: send a byte from a terminal, receive it back. A satisfying end-to-end demo. | Baseline D12 daily plan | UART TX + RX |
| SPI Master | SPI protocol, clock polarity/phase, FSM-driven shifting, talking to a real sensor. | Baseline D12 daily plan (RX & SPI) | D7 FSMs, D11 UART |
| High-complexity projects | The three project options held back from the abroad list because they need more structured time than one build day allows. | See below | Varies |
Stretch project options (not on the abroad 6-option list)¶
These were removed from the rescoped project options because each needs more than the single in-class build day. They make excellent self-directed or follow-on projects:
| Project | Key Concepts | Difficulty |
|---|---|---|
| SPI Sensor Interface | SPI master + FSM + data parsing | ★★★ |
| VGA Pattern Display | Timing-critical VGA + frame buffer | ★★★ |
| Simple Processor | ALU + register file + FSM sequencer (conceptually previewed in the RISC-V guest lecture) | ★★★ |
Where to go after the course¶
- UVM & constraint-random verification — the industry-standard methodology that SV assertions and coverage lead into.
- Formal verification — proving properties hold for all inputs, not just tested cases.
- RISC-V — David Castells Rufas' guest lecture is the on-ramp; the open ISA is the place to apply everything from FSMs to memory to UART.
- ASIC/FPGA career paths — covered in the Demo Day wrap (D16).