CRAFT Slide Decks¶

In-class decks for the Barcelona abroad edition · SystemVerilog decks moved to optional self-study

Each deck walks the CRAFT cycle — Contextualize → Reframe → Assemble → Fortify → Transfer — for a single 2.5-hour class day. The decks are paired with the underlying baseline daily plans and the Barcelona CRAFT overlays.

Time allocation

The bulk of every 2.5-hour session sits in Assemble + Fortify (~115 min total). The merged D1+D2 Monday is the exception — Reframe runs longer because we walk every student through toolchain setup and the first board upload, and the combined lab spills into the Tuesday catch-up block.

Week 1 · Verilog Foundations¶

DAY 01+02 · Mon 5/25 (pt 1)

Hardware Thinking

Merged session · Reframe extended for setup · CRAFT debut

DAY 01+02 · Mon 5/25 (pt 2)

Data Types, Vectors & Operators

Merged session · lab finished Tue 5/26 catch-up

DAY 03 · Wed 5/27

Combinational Logic & always@(*)

Latch hunt · ALU · first PPA · PM: Sagrada Família

DAY 04 · Fri 5/29

Clocked Logic & RTL Thinking

D-FF · counter · blinker · 🤖 AI thread starts

Week 2 · Sequential Design & Verification¶

DAY 05+06 · Mon 6/1

Counters, Testbenches & AI Verification

Merged session · debouncer · 🤖 AI TB · PM: Semidynamics

DAY 07 · Tue 6/2

Finite State Machines

3-block pattern · traffic light · pattern detector · PM: HP

DAY 08 · Wed 6/3

Hierarchy, Parameters & Generate

Param families · PPA width sweep · Eve: Cooking

Thu 6/4 — catch-up day

No deck: Thursday is a lab catch-up block — finish this week's labs. Project selection is due Tue 6/9 (Week 3). Memory (D9) moves to Week 3.

Week 3 · Memory, Timing & Communication¶

DAY 09 · Mon 6/8

Memory: RAM, ROM & Block RAM

Moved from Week 2 · EBR inference · $readmemh

DAY 10 · Tue 6/9

Timing, Numerical Architectures & PPA

Adders · shift-add mult · Q4.4 · nextpnr Fmax · Eve: Flamenco

DAY 11 · Wed 6/10

UART: Protocol Design & Implementation

Condensed · "HELLO" on terminal · PM: Park Güell

Thu 6/11 — project build/catch-up day

No deck: Thursday is structured project build + lab catch-up (one of the two slots freed by removing the SystemVerilog days).

Beyond the scope — optional self-study decks¶

These SystemVerilog decks are not scheduled in the Barcelona edition. They are kept as optional resources for the Keep Going self-study track.

OPTIONAL · Self-study

SystemVerilog for Design

logic · always_ff · enum

OPTIONAL · Self-study

SystemVerilog for Verification

Assertions · AI TB capstone

Week 4 · Integration & Demonstration¶

DAY 14 · Tue 6/16

Project Build Day

3 checkpoints · PPA · 🤖 AI TB · hardware-on-board

DEMO · Thu 6/18

Demos & Course Wrap

5-min demos · AI portfolio share-out · retrospective

Week 4 — the CRAFT shift

Week 4 days are non-standard (visit, build, guest, demo) so the time allocation shifts while the cycle stays. The "bulk on Assemble + Fortify" rule still holds — but Assemble means the visit, the build session, the guest lecture, or the demos themselves. Fortify is the immediate post-event synthesis: reflection, PPA, peer feedback, retrospective.

Using the decks¶

Open in presentation mode — the decks are reveal.js. Press F for fullscreen, Esc to overview, arrow keys (or space) to navigate, and S to open the speaker-notes window.
Black title slides mark each CRAFT phase and show how long it runs — useful as in-class checkpoints when moving from Assemble into Fortify.
The phase bar (C R A F T) appears on title slides; all five glow gold because every day visits every phase.
Time pills (e.g. Ex 2 · 15 min) come straight from the baseline daily plan and the CRAFT overlays.

Companion resources¶

The full lab guide for each day lives at docs_src/days/dayNN/lab.md — keep it open alongside the deck.
The Barcelona-specific overlay (one-page Contextualize / Reframe / Transfer cues) lives at barcelona/craft/dayNN_craft.md.
Pre-class videos and quizzes are linked from each day's overview page in the main site nav.

Back to Barcelona index