Day 13: SystemVerilog for Design¶

Week 4 · Session 13 of 16

Daily Plan

Session timeline & instructor notes

Lab Guide

4 exercises · hands-on

Pre-Class Quiz

Self-check questions

Starter Code

All exercises bundled

Pre-Class Slide Decks¶

Work through the slide decks below to prepare for this session. Each deck's focus is summarized so you can see what's ahead at a glance.

Twelve days of pure Verilog behind you. Time to learn the superset you'll actually write in your career.

One type. Replaces both wire and reg. End of a whole category of bugs.

The block you write tells the tool what hardware you want. The tool then enforces it. Bugs caught at compile time.

The features that make your codebase look like software engineering rather than a pile of Verilog files.

Code shown during the pre-class video. Each example is a runnable

subdirectory with its own Makefile (make sim, make stat, make prog).

d13_s2_ex1 — browse
- day13_ex01_debounce_sv.sv
- tb_debounce_sv.sv
d13_s3_ex2 — browse
- day13_ex02_uart_tx_sv.sv
- tb_uart_tx_sv.sv
d13_s4_ex3 — browse
- day13_ex03_traffic_light_sv.sv
- tb_traffic_light_sv.sv