Day 14 Lab: Verification Techniques, AI-Driven Testing & PPA Analysis¶
Starter Code
Download All Starter Code (.zip)
Individual exercise downloads and file links are below each exercise.
Overview¶
The capstone verification session — all four cross-cutting threads converge. You'll add assertions to existing designs, implement a constraint-based UART parity extension, generate AI-driven testbenches for your project, and produce a structured PPA analysis.
Prerequisites¶
- Pre-class videos on assertions, AI verification workflows, PPA methodology, and coverage
- Working UART TX (SV version from Day 13 or Verilog from Day 11)
- Working FSM from Day 7 or Day 13
- Final project module (at least the interface defined) for Exercise 3
Toolchain Notes¶
- Immediate assertions: supported by
iverilog -g2012 - Concurrent assertions: NOT supported by Icarus (write as documentation only)
- Covergroups: NOT supported by Icarus (manual analysis in Exercise 4)
Exercises¶
Checking your work. Run
make testfrom inside an exercise'sstarter/directory to compare your DUT against the reference and get a PASS/FAIL — no flags or unlocking. If you want to see the worked answer, it is in that exercise's../solution/ref/.
| # | Exercise | Time | Key SLOs |
|---|---|---|---|
| 1 | Assertion-Enhanced UART TX | 25 min | 14.1 |
| 2 | Constraint-Based UART Parity Extension | 20 min | 14.2, 14.4 |
| 3 | AI Constraint-Based TB for Project Module | 25 min | 14.3, 14.6 |
| 4 | PPA Analysis Exercise | 25 min | 14.4, 14.5 |
| 5 | Project Work Time | 15 min | — |
Ex 1 — UART Assertions¶
- Self-check:
cd ex1_uart_assertions/starter && make test— passes when your output matches the reference - (Optional) Reference: the worked answer is in
../solution/ref/. - What the grader checks: the gate confirms your assertions run clean against the correct DUT — a mis-specified assertion that false-fires will fail. Because a passing assertion produces no output, the grader cannot confirm you wrote all seven; demonstrate completeness with the bug-injection step (inject a fault and show the matching assertion fires).
Ex 2 — UART Parity¶
- Self-check:
cd ex2_uart_parity/starter && make test— passes when your output matches the reference - What the grader checks: the provided testbench decodes the serial frame on both the
no-parity and even-parity instances and verifies its structure (start + 8 data +
[parity] + stop) and the parity bit. It passes only once your
generate ifparity implementation produces correct frames — a stub that never sends the parity bit fails the frame checks. - (Optional) Reference: the worked answer is in
../solution/ref/.
Ex 3 — AI Constraint TB¶
- Note: This exercise has no automated
make testgrader — its reference solution ships unencrypted insolution/.
Ex 4 — PPA Analysis¶
- Note: This exercise has no automated
make testgrader — its reference solution ships unencrypted insolution/.
Instructor note: Exercise 2 has an escape valve — those behind on their final project may skip it and use the time for Exercises 3–4. Parity can be completed as homework.
Deliverables¶
- Assertion-enhanced UART TX with 7 assertions + bug injection demo
- Parity-parameterized UART TX with PPA comparison (PARITY_EN=0 vs 1)
- AI constraint-based TB with: constraint spec + raw AI output + corrected TB + coverage analysis
- PPA analysis report — comparison table with real data + 2 analysis paragraphs
Supplementary Material¶
The following exercises from the original Day 14 build are available as supplementary content for those who finish early or want additional practice:
supplementary/fsm_assertions/— Add transition and output assertions to the traffic light FSMsupplementary/coverage_worksheet/— Manual functional coverage analysis for the ALU
Shared Resources¶
go_board.pcf— Pin constraint file- Reuse modules from
shared/lib/for PPA analysis targets
Build Commands Quick Reference¶
# ── from labs/week4_day14/exN_*/starter/ ──
make test # run published self-checking testbench (PASS/FAIL)