Barcelona Schedule
Summer 2026 — HDL for Digital System Design Abroad
This page shows the Barcelona-adapted course calendar. The baseline
16-day curriculum is trimmed to a focused set of teaching sessions plus
academic visits and a guest lecture. SystemVerilog and other advanced
topics move to a guided self-study track — see
Keep Going: Beyond the Scope of This Course.
For the full adaptation plan, see the
Barcelona Adaptation Document.
Calendar Overview
Week 1: Verilog Foundations (May 25–29)
| Date |
Type |
Session |
| Mon 5/25 |
Merged |
D1+D2: Hardware Thinking + Data Types, Vectors & Operators |
| Tue 5/26 |
Catch-up |
Setup completion + combined D1+D2 lab finish |
| Wed 5/27 |
Class |
D3: Combinational Logic · PM: Sagrada Familia |
| Thu 5/28 |
Excursion |
Montserrat Day Trip |
| Fri 5/29 |
Catch-up |
Combinational lab catch-up + Week 2 prep (D4 moved to Week 2) |
Week 2: Sequential Design & Verification (Jun 1–5)
| Date |
Type |
Session |
| Mon 6/1 |
Class |
D4: Clocked Logic & RTL Thinking · PM: Semidynamics |
| Tue 6/2 |
Merged |
D5+D6: Counters, Testbenches & AI Verif |
| Wed 6/3 |
Class |
D7: FSMs · Eve: Cooking |
| Thu 6/4 |
Class |
D8: Hierarchy & Parameters · PM: HP Barcelona |
| Fri 6/5 |
Catch-up |
Lab catch-up + Week 3 prep (Memory moved to Week 3) |
Week 3: Memory, Timing & Communication (Jun 8–12)
| Date |
Type |
Session |
| Mon 6/8 |
Class |
D9: Memory: RAM, ROM & Block RAM (moved from Week 2) |
| Tue 6/9 |
Class |
D10: Timing & Numerical Architectures · Project selection due · Eve: Flamenco |
| Wed 6/10 |
Condensed |
D11: UART TX (RX = stretch) · PM: Park Güell |
| Thu 6/11 |
Project |
Project build + lab catch-up |
| Fri 6/12 |
Free |
Independent project work |
Week 4: Integration & Demonstration (Jun 15–19)
| Date |
Type |
Session |
| Mon 6/15 |
Visit |
Barcelona Metro Control Room |
| Tue 6/16 |
Class |
D14: Project Build Day |
| Wed 6/17 |
Guest |
RISC-V Lecture — David Castells Rufas |
| Thu 6/18 |
Class |
D15: Demos & Course Wrap |
| Fri 6/19 |
Free |
Departure / free day |
Key Dates
- Project selection: Tue 6/9
- Core module due: Thu 6/11
- Build day: Tue 6/16
- Demo day: Thu 6/18