Final Project — Barcelona Abroad Edition¶

Overview¶

Design, simulate, and demonstrate a small digital system on the Nandland Go Board. The project is deliberately scoped to fit a single build day plus independent work — pick a scaffold, complete it, verify it, and demo it.

Every option exercises the same three core skills:

Build out an FSM — a real control state machine.
Extend a testbench — the shipped testbench already runs and self-checks; you grow it into real verification.
Implement sequential and combinational logic — usually inside the FSM.

Work in teams

The final project is a team project (2–3 people). Each scaffold's SPEC.md suggests a Control / Datapath / Verification split so everyone owns a piece, and the demo is a shared result. Solo is allowed if you'd rather; the deliverables are the same.

Scaffolds — start here¶

You don't start from a blank file. Each project ships as a self-contained directory under projects/barcelona/ in your lab repo, containing:

File	What it is
`SPEC.md`	Specification sheet — behaviour, board I/O, what to build, team split
`TESTPLAN.md`	Verification sheet — scenarios, coverage checklist, extension ideas
`<project>.v`	The core module you build — an FSM scaffold with `TODO` blocks
`top_<project>.v`	Board wiring (drives both 7-seg displays) — already complete
`tb_<project>.v`	Self-checking testbench: a few active checks + commented scenarios
`Makefile`, `go_board.pcf`	Build + flash; library modules copied in (self-contained)

The scaffold compiles and the testbench runs from day one — it just sits in its reset state until you fill the TODOs. So make sim works immediately and you build up from a known-good baseline.

cp -r projects/barcelona/combo_lock ~/my_project
cd ~/my_project
make sim         # passes the reset checks out of the box
# read SPEC.md → fill the TODOs → uncomment the TESTPLAN scenarios
make             # synthesize        make prog        # flash the board

Project options (choose one)¶

Simplified options¶

#	Project	Key idea	Difficulty
1	Dice Roller (`dice_roller`)	Hold to spin two dice; release to settle on 1–6	★☆☆
2	Combination Lock (`combo_lock`)	Open a lock by pressing 3 buttons in the secret order	★★☆
3	Reaction Timer (`reaction_timer`)	Wait for the light, then react as fast as you can	★★☆
4	Stopwatch (`stopwatch`)	Start/stop a two-digit 00–99 s stopwatch	★★☆

Stretch options¶

#	Project	Key idea	Difficulty
5	Digital Clock (`digital_clock`)	00–59 s clock with a SET mode	★★☆
6	Pattern Generator (`pattern_generator`)	LFSR light show: run / pause / single-step	★☆☆
7	Tone Generator (`tone_generator`)	8-note melody on a piezo speaker (PMOD)	★★☆
8	UART Command Parser (`uart_command_parser`)	Parse two-byte serial commands and act	★★☆
9	Game of Life (`game_of_life`)	1-D cellular automaton on a wrapped 8-cell row	★★★

You may propose a custom project with instructor approval — it just has to exercise the three skills above (one FSM, an extended testbench, and sequential + combinational logic).

The Go Board has two 7-segment displays

Every scaffold drives both (o_segment1_* and o_segment2_* — see shared/pcf/go_board.pcf). Use both digits in your design.

Want something bigger?

Higher-complexity builds (SPI sensor interface, VGA pattern display, a small processor, a full 2-D Conway grid in block RAM) make excellent self-directed extensions — see Keep Going: Beyond the Scope.

Timeline¶

Date	Milestone
Tue 6/9	Team + project selection due
Wed 6/10	Block diagram + module list (1-page sketch); scaffold copied, `make sim` green
Thu 6/11	Core FSM compiles + simulates; first new testbench scenario passing
Fri 6/12 – Mon 6/15	Independent work (weekend + Metro visit day afternoon)
Tue 6/16	Build day: integration, hardware bring-up, PPA
Wed 6/17 afternoon	Independent polish (after RISC-V lecture)
Thu 6/18	Demo day — 5-min demo + 2-min Q&A; all deliverables due

Deliverables¶

Working hardware demo (5 min) — running on the Go Board, both 7-seg displays driven, demonstrated live by the team.
Source code — completed <project>.v following course conventions (i_/o_/r_/w_ prefixes), plus your top and any helper modules.
An extended testbench — start from the shipped tb_<project>.v: enable the commented TODO scenarios and add at least one of your own. Walk the TESTPLAN.md coverage checklist.
PPA snapshot — make stat (LUT + FF counts) with one or two sentences on what dominates the resource use.
Team note — a few sentences: who owned what, and one thing you'd do next.

Project grading¶

The final project is worth 10% of the course grade. Within the project, components are weighted as follows:

Component	Weight
Working hardware demo (both displays)	35%
Code quality & conventions	20%
Testbench — scenarios enabled + your own + coverage	25%
PPA snapshot + team note	10%
Live demo presentation	10%

For the full course grading breakdown, see the Barcelona Day Plan.

Tips¶

Start with the FSM. Every scaffold's core work is the next-state logic. Get the state machine right in simulation first, then wire up the datapath.
Use make sim constantly. It runs out of the box, so you always have a green baseline — re-run it after every small change.
Enable one TESTPLAN scenario per feature. As you implement a TODO in the design, uncomment the matching testbench scenario and watch it pass.
Reuse course modules. debounce, hex_to_7seg, edge_detect, uart_tx are already copied into each scaffold — and live in the shared library.
Use AI to verify, not to design. Ask an AI tool to generate extra test stimulus, then read it critically and keep what adds coverage.