Day 5: Counters, Shift Registers & Debouncing¶
Week 2 · Session 5 of 16
Pre-Class Slide Decks¶
Work through the slide decks below to prepare for this session. Each deck's focus is summarized so you can see what's ahead at a glance.
Segment 1: Counter Variations¶
Topic 4 gave you the basic free-running counter. Today we cover the variations you'll use in practice: modulo-N, up/down, loadable.
Segment 2: Shift Registers¶
Shift registers: how streams of serial bits become parallel words, and vice versa. These are the pattern behind every serial protocol.
Segment 3: Metastability Synchronizers¶
The most-ignored, highest-stakes concept in synchronous design. By the end of this video you'll know why every professional design has two flops guarding every asynchronous input.
Segment 4: Button Debouncing¶
The capstone: combining the previous topic's synchronizer with a debounce counter to produce the universal input-processing pipeline.
Lecture Code Examples¶
Code shown during the pre-class video. Each example is a runnable
subdirectory with its own Makefile (make sim, make stat, make prog).