Day 10: Numerical Architectures & PPA¶
Week 3 · Session 10 of 16
Pre-Class Slide Decks¶
Work through the slide decks below to prepare for this session. Each deck's focus is summarized so you can see what's ahead at a glance.
Segment 1: Timing Essentials¶
Timing: the one thing the synthesizer tells you whether your design is fast enough.
Segment 2: Numerical Architectures¶
What + and * actually build — the architectures behind the operators.
Segment 3: Ppa Intro¶
The three-axis framework every real design is evaluated on.
Segment 4: Asic Ppa Context¶
What happens when your Verilog becomes a real chip.
Lecture Code Examples¶
Code shown during the pre-class video. Each example is a runnable
subdirectory with its own Makefile (make sim, make stat, make prog).