Day 11: UART TX: Communication Interface¶
Week 3 · Session 11 of 16
Pre-Class Slide Decks¶
Work through the slide decks below to prepare for this session. Each deck's focus is summarized so you can see what's ahead at a glance.
Segment 1: Uart Protocol¶
The oldest, simplest, and most widely deployed serial protocol — still used everywhere in 2026.
Segment 2: Uart Tx Architecture¶
How the UART transmitter decomposes into an FSM + datapath.
Segment 3: Uart Tx Implementation¶
Build the UART TX in Verilog from scratch.
Segment 4: Connecting To Pc¶
Crossing the boundary: your Verilog talks to software on a computer.
Lecture Code Examples¶
Code shown during the pre-class video. Each example is a runnable
subdirectory with its own Makefile (make sim, make stat, make prog).