CRAFT Overlay — D8 — Hierarchy, Parameters & Generate¶

Date: Wed 6/3

🌍 Contextualize¶

"Parameterized design is how companies build IP libraries. Semidynamics doesn't redesign their RISC-V core for each customer — they parameterize it."

⚠️ Reframe¶

"If You're Thinking Like a Programmer: copy-paste is reuse. Reframe: Parameterized modules + generate create hardware at elaboration time, not at runtime. generate for unrolls into parallel hardware."

🔑 Key Insight¶

"generate doesn't loop at runtime — it creates hardware at synthesis time. A generate for with N=4 creates 4 physical instances, not one instance used 4 times."

🤖 Check the Machine¶

"Prompt AI to generate a parameterized N-bit comparator with generate. Does it use generate correctly? Synthesize at WIDTH=8, 16, 32 and compare yosys stat — is area scaling linear?"

🔗 Transfer¶

"Tomorrow is a catch-up day — finish this week's labs and start scoping your project (final selection is due Tue 6/9, in Week 3). Memory moves to next week: Monday 6/8 opens Week 3 with ROM, RAM, and the coding patterns that make Yosys infer block RAM instead of burning all your LUTs."

Visit/Activity Connection¶

Evening: Cooking Workshop — A recipe is sequential (step by step). A kitchen with multiple cooks is parallel — like HDL.

Back to Barcelona Day Plan View Slides Baseline D8 Materials

This overlay supplements the baseline D8 daily plan. All lab exercises and lecture content come from the baseline D8 materials.