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HDL for Digital System Design — Barcelona Abroad

UCF Study Abroad · Barcelona, Spain · Summer 2026

The HDL curriculum, trimmed and adapted for a study-abroad format: 11 focused teaching sessions, dedicated catch-up/build days, 3 academic visits, a guest RISC-V lecture, and the CRAFT pedagogical overlay woven into every session. Advanced topics (SystemVerilog and more) live in a guided self-study track.

11
Teaching Sessions
D1+D2 & D5+D6 merged · 4 catch-up/build days
3+1
Academic Visits
+ RISC-V guest lecture
CRAFT
Pedagogy
Every session, every visit
iCE40
FPGA Platform
Nandland Go Board

Weekly Arc

1 Verilog Foundations (May 25–29)
DAY 01+02
Hardware Thinking + Data Types, Vectors & Operators
Merged · Mon 5/25 · Lab Setup + first board upload
DAY 01+02
Hardware Thinking + Data Types, Vectors & Operators
Merged · Mon 5/25 · Lab Setup + first board upload
DAY 03
Combinational Logic
PM: Sagrada Familia
EXCURSION
Montserrat Day Trip
Thu 5/28
CATCH-UP
Combinational Lab Catch-up + Week 2 Prep
Fri 5/29
3 Memory, Timing & Communication (Jun 8–12)

Academic Visits & Enrichment

Semidynamics (Jun 1 PM)

RISC-V vector processor startup — see how RTL meets commercial silicon design in a Barcelona fab-adjacent company.

HP Barcelona (Jun 4 PM)

Large-scale hardware verification and test infrastructure at a major semiconductor site.

Barcelona Metro Control Room (Jun 15)

Real-time embedded systems managing a city's transit network — digital design in critical infrastructure.

RISC-V Guest Lecture (Jun 17)

David Castells Rufas on open-source ISA design — connecting course HDL skills to the RISC-V ecosystem.

Course Grading

Component Weight What Counts
Attendance & Activities 20% Daily attendance + in-class participation/activities
Lab Exercises 60% Completed daily lab upload (one per teaching session, ~9 labs)
Final Project 10% Self-selected Verilog project, demo + source + testbench + PPA report
Tour & Guest Lecture Reflections 5% Short reflections after each industry visit + RISC-V guest lecture
Cultural Activity Reflections 5% Short reflections on Barcelona cultural activities (Sagrada Familia, Montserrat, Flamenco, Park Güell, cooking, etc.)
Total 100%

See the Barcelona Project Spec for project-specific deliverables and rubric.

What Makes the Abroad Edition Different

CRAFT Pedagogy in Every Session

Contextualize → Reframe → Assemble → Fortify → Transfer. Each 2.5-hour session follows this research-backed cycle.

Industry Context on Location

Academic visits replace textbook motivation — you see HDL concepts in production before you build them in lab.

Focused Scope, Guided Beyond

11 teaching sessions cover the core HDL arc. Two merges (D1+D2, D5+D6) and a trimmed scope keep the pace humane; SystemVerilog and advanced topics live in a guided self-study track.

Open-Source Everything

No license servers, no vendor lock-in — the same iCE40 toolchain travels with you.

Discussion

Discussion