CRAFT Overlay — D13 — SystemVerilog for Verification¶

Beyond the scope of the Barcelona edition — self-study

SystemVerilog is not a scheduled day in the Barcelona abroad edition. This overlay is kept as an optional resource in the Keep Going self-study track. Work through it on your own using the baseline D14 materials and the optional V14 video.

🌍 Contextualize¶

"Assertions are executable specifications. In industry, the verification engineer writes assertions before the designer writes RTL. When the design violates a property, the assertion fires immediately — not after hours of waveform debugging."

⚠️ Reframe¶

"If You're Thinking Like a Programmer: testing is something you do at the end. Reframe: Assertions live inside your design. They fire the instant something goes wrong. They're not tests — they're contracts."

🔑 Key Insight¶

"An assertion that never fires might mean your design is correct — or it might mean your testbench never exercises that path. Coverage tells you which."

🤖 Check the Machine¶

"Prompt AI to add 5 assertions to your UART TX module. Run them. Do any fire? Then ask AI to generate stimulus that should trigger each assertion. This is constraint-based testing."

🔗 Transfer¶

"Assertions and coverage are the on-ramp to UVM and formal verification — the industry-standard methodologies. See the Keep Going section for where to take this next."

Back to Barcelona Day Plan View Slides Baseline D14 Materials

This overlay supplements the baseline D14 daily plan (SV Verification). All lab exercises and lecture content come from the baseline D14 materials.