Day 7: Finite State Machines¶
Week 2 · Session 7 of 16
Pre-Class Slide Decks¶
Work through the slide decks below to prepare for this session. Each deck's focus is summarized so you can see what's ahead at a glance.
Segment 1: Fsm Theory Architecture¶
Welcome to Video 1 of 4 for Topic 7 — Finite State Machines. This is arguably the most important concept in the second half of this course. Every protocol controller, every memory arbiter, every bus interface you will design for the rest of your career is fundamentally an FSM. This video is about 14 minutes. Keep a text editor open — we'll build an FSM together.
Segment 2: Three Block Template¶
Yesterday you saw FSM theory — state diagrams, Moore vs Mealy. Today you learn the single Verilog pattern that implements them reliably.
Segment 3: State Encoding¶
One of the few Verilog decisions that visibly changes silicon cost.
Segment 4: Fsm Design Methodology¶
The process for turning a specification into a working FSM. Put into practice with a pattern detector.
Lecture Code Examples¶
Code shown during the pre-class video. Each example is a runnable
subdirectory with its own Makefile (make sim, make stat, make prog).